參數(shù)資料
型號: 74HC4020PW,118
廠商: NXP Semiconductors
文件頁數(shù): 5/7頁
文件大?。?/td> 0K
描述: IC 14STAGE BINARY RIPPLE 16TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,500
系列: 74HC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 14
復(fù)位: 異步
計(jì)數(shù)速率: 109MHz
觸發(fā)器類型: 負(fù)邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
1998 Jul 08
5
Philips Semiconductors
Product specication
Hex D-type ip-op with reset; positive-edge trigger
74HC/HCT174
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP to Qn
55
165
205
250
ns
2.0
Fig.6
20
33
41
50
4.5
16
28
35
43
6.0
tPHL
propagation delay
MR to Qn
44
150
190
225
ns
2.0
Fig.7
16
30
38
45
4.5
13
26
33
38
6.0
tTHL/ tTLH
output transition time
19
75
95
110
ns
2.0
Fig.6
7
15
19
22
4.5
6
13
16
19
6.0
tW
clock pulse width
HIGH or LOW
80
17
100
120
ns
2.0
Fig.6
16
6
20
24
4.5
14
5
17
20
6.0
tW
master reset pulse
width; LOW
80
12
100
120
ns
2.0
Fig.7
16
4
20
24
4.5
14
3
17
20
6.0
trem
removal time
MR to CP
5
11
5
ns
2.0
Fig.7
5
4
5
4.5
5
3
5
6.0
tsu
set-up time
Dn to CP
60
6
75
90
ns
2.0
Fig.8
12
2
15
18
4.5
10
2
13
15
6.0
th
hold time
Dn to CP
3
6
3
ns
2.0
Fig.8
3
2
3
4.5
3
2
3
6.0
fmax
maximum clock pulse
frequency
6
30
5
4
MHz
2.0
Fig.6
30
90
24
20
4.5
35
107
28
24
6.0
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