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參數(shù)資料
| 型號： | 74HC4017PW,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC JOHNSON DECADE COUNT 16TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 系列： | 74HC |
| 邏輯類型： | 計(jì)數(shù)器，十進(jìn)制 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 10 |
| 復(fù)位： | 異步 |
| 計(jì)數(shù)速率： | 83MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 2 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 74HC4017PW 74HC4017PW-ND 935189080112 |
74HC_HCT4017
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 10 December 2013
14 of 24
NXP Semiconductors
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
12. Application information
Some examples of applications for the 74HC4017; 74HCT4017 are:
Decade counter with decimal decoding
1 out of n decoding counter (when cascaded)
Sequential controller
Timer
Figure 12 shows a technique for extending the number of decoded output states for the
74HC4017; 74HCT4017. Decoded outputs are sequential within each stage and from
stage to stage, with no dead time (except propagation delay).
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 11. Load circuitry for measuring switching times
VM
tW
10 %
90 %
0 V
VI
negative
pulse
positive
pulse
0 V
VM
90 %
10 %
tf
tr
tf
001aad983
DUT
VCC
VI
VO
RT
RL
S1
CL
open
G
Table 9.
Test data
Type
Input
Load
S1 position
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
74HC4017
VCC
6ns
15pF, 50 pF
1k
open
GND
VCC
74HCT4017
3 V
6 ns
15 pF, 50 pF
1 k
open
GND
VCC
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