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參數(shù)資料
| 型號： | 74HC40104 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 4-bit bidirectional universal shift register; 3-state |
| 中文描述： | 4位雙向通用移位寄存器;三態(tài) |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 62K |
| 代理商： | 74HC40104 |
December 1990
2
Philips Semiconductors
Product specification
4-bit bidirectional universal shift
register; 3-state
74HC/HCT40104
FEATURES
Synchronous parallel or serial operating
3-state outputs
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT40104 are high-speed Si-gate CMOS
devices and are pin compatible with the “40104” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT40104 are universal shift registers
featuring parallel inputs, parallel outputs, shift-right and
shift-left serial inputs and 3-state outputs allowing the
devices to be used in bus-organized systems.
In the parallel-load mode (S
0
and S
1
are HIGH), data is
loaded into the associated flip-flop and appears at the
output after the positive transition of the clock input (CP).
During loading, serial data flow is inhibited. Shift-right and
shift-left are accomplished synchronously on the positive
clock edge with serial data entered at the shift-right (D
SR
)
and shift-left (D
SL
) serial inputs, respectively.
Clearing the register is accomplished by setting both mode
controls (S
0
and S
1
) LOW and clocking the register. When
the output enable input (OE) is LOW, all outputs assume
the high-impedance OFF-state (Z).
APPLICATIONS
Arithmetic unit bus registers
Serial/parallel conversion
General-purpose register for bus organized systems
General-purpose registers
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
f
max
C
I
C
PD
propagation delay CP to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
13
62
3.5
75
15
57
3.5
75
ns
MHz
pF
pF
notes 1 and 2
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|---|---|
| 74HCT40105 | 8-Bit Parallel-Load Shift Registers 16-SOIC -40 to 85 |
| 74HCT40105PW | 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85 |
| 74HC40105 | 4-bit x 16-word FIFO register |
| 74HCT4015 | 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85 |
| 74HC4015 | Dual 4-bit serial-in/parallel-out shift register |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74HC40105D | 功能描述:寄存器 4BX16W FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HC40105D,652 | 功能描述:寄存器 4BX16W FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HC40105D,653 | 功能描述:寄存器 4-BIT X 16 WORD FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HC40105D652 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| 74HC40105DB | 功能描述:寄存器 4-BIT X 16 WORD FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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