參數(shù)資料
型號(hào): 74HC40103D
元件分類(lèi): 通用總線功能
英文描述: 8-bit synchronous binary down counter
中文描述: 8位同步二進(jìn)制計(jì)數(shù)器下降
文件頁(yè)數(shù): 8/17頁(yè)
文件大?。?/td> 136K
代理商: 74HC40103D
1998 Jul 08
8
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
I
CC
category: MSI
Note to HCT types
The value of additional quiescent supply current (
I
CC
) for a unit load of 1 is given in the family specifications.
To determine
I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
INPUT
UNIT LOAD COEFFICIENT
CP, PE
MR
TE
PL
P
n
1.50
1.00
0.80
0.35
0.25
SYMBOL
PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+
25
40 to
+
85
40 to
+
125
min. typ.
max.
min.
max. min.
max.
t
PHL
/ t
PLH
propagation delay
CP to TC
propagation delay
TE to TC
propagation delay
PL to TC
propagation delay
MR to TC
output transition time
35
60
75
90
ns
4.5
Fig.7
t
PHL
/ t
PLH
23
40
50
60
ns
4.5
Fig.8
t
PHL
/ t
PLH
44
75
94
112
ns
4.5
Fig.9
t
PHL
29
55
69
83
ns
4.5
Fig.9
t
THL
/ t
TLH
7
15
19
22
ns
4.5
Figs. 7 and 8
t
W
clock pulse width
HIGH or LOW
master reset pulse width
LOW
preset enable pulse width
PL; LOW
removal time
MR to CP or PL to CP
set-up time
PE to CP
set-up time
TE to CP
33
10
41
50
ns
4.5
Fig.7
t
W
30
16
38
45
ns
4.5
Fig.9
t
W
38
22
48
57
ns
4.5
Fig.9
t
rem
10
1
13
15
ns
4.5
Fig.10
t
su
20
11
25
30
ns
4.5
Fig.11
t
su
40
20
50
60
ns
4.5
Fig.11
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