參數(shù)資料
型號(hào): 74HC40103D,653
廠商: NXP Semiconductors
文件頁(yè)數(shù): 9/25頁(yè)
文件大?。?/td> 0K
描述: IC 8BIT SYNC BINARY DOWN 16SOIC
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,500
系列: 74HC
邏輯類(lèi)型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
復(fù)位: 異步
計(jì)時(shí): 同步
計(jì)數(shù)速率: 32MHz
觸發(fā)器類(lèi)型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SO
包裝: 帶卷 (TR)
其它名稱(chēng): 74HC40103D-T
74HC40103D-T-ND
933714730653
9397 750 13812
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
17 of 25
Philips Semiconductors
74HC40103
8-bit synchronous binary down counter
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
VM = 0.5 × VI.
Fig 11. Waveforms showing hold and set-up times for
Pn, PE to CP
Fig 12. Waveforms showing hold and set-up times for
MR or PE to CP
VM
stable
001aab931
PE input
CP input
P0 to P7
input
tsu
th
VM
tsu
th
001aab930
TE or PE
input
CP input
VM
tsu
th
VM
Test data is given in Table 9.
Denitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 13. Load circuitry for switching times
Table 9:
Test data
Supply
Input
Load
VCC
VI
tr, tf
CL
2.0 V
VCC
6 ns
50 pF
4.5 V
VCC
6 ns
50 pF
6.0 V
VCC
6 ns
50 pF
5.0 V
VCC
6 ns
15 pF
mna101
VCC
VI
VO
RT
CL
PULSE
GENERATOR
D.U.T.
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