參數(shù)資料
型號(hào)： 74HC3G07
廠商： NXP Semiconductors N.V.
英文描述： Buffer with open-drain outputs
中文描述： 緩沖區(qū)為開漏輸出
文件頁(yè)數(shù)： 2/17頁(yè)
文件大小： 82K
代理商： 74HC3G07
2003 Oct 30
2
Philips Semiconductors
Product specification
Inverter
74HC3G04; 74HCT3G04
FEATURES
Wide supply voltage range from 2.0 to 6.0 V
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
Very small 8 pins package
Output capability: standard
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74HC3G/HCT3G04 is a high-speed Si-gate CMOS
device and is pin compatible with low power Schottky
TTL (LSTTL). Specified in compliance with JEDEC
standard no. 7.
The 74HC3G/HCT3G04 provides three inverting buffers.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
6.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total switching outputs;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
For HC3G04 the condition is V
I
= GND to V
CC
.
For HCT3G04 the condition is V
I
= GND to V
CC
1.5 V.
2.
FUNCTION TABLE
See note 1.
Note
1.
H = HIGH voltage level;
L = LOW voltage level.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC3G04
HCT3G04
t
PHL
/t
PLH
C
I
C
PD
propagation delay nA to nY
input capacitance
power dissipation capacitance per buffer
C
L
= 50 pF; V
CC
= 4.5 V 8
10
1.5
9
ns
pF
pF
1.5
9
notes 1 and 2
INPUT
OUTPUT
nA
nY
L
H
H
L
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