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參數資料
| 型號： | 74HC390 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual decade ripple counter |
| 中文描述： | 雙十年紋波計數器 |
| 文件頁數： | 2/7頁 |
| 文件大?。?/td> | 49K |
| 代理商： | 74HC390 |
December 1990
2
Philips Semiconductors
Product specification
Dual decade ripple counter
74HC/HCT390
FEATURES
Two BCD decade or bi-quinary counters
One package can be configured to divide-by-2, 4, 5, 10,
20, 25, 50 or 100
Two master reset inputs to clear each decade counter
individually
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT390 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT390 are dual 4-bit decade ripple counters
divided into four separately clocked sections. The counters
have two divide-by-2 sections and two divide-by-5
sections. These sections are normally used in a BCD
decade or bi-quinary configuration, since they share a
common master reset input (nMR). If the two master reset
inputs (1MR and 2MR) are used to simultaneously clear all
8 bits of the counter, a number of counting configurations
are possible within one package. The separate clocks
(nCP
0
and nCP
1
) of each section allow ripple counter or
frequency division applications of divide-by-2, 4, 5, 10, 20,
25, 50 or 100.
Each section is triggered by the HIGH-to-LOW transition of
the clock inputs (nCP
0
and nCP
1
). For BCD decade
operation, the nQ
0
output is connected to the nCP
1
input
of, the divide-by-5 section. For bi-quinary decade
operation, the nQ
3
output is connected to the nCP
0
input
and nQ
0
becomes the decade output.
The master reset inputs (1MR and 2MR) are active HIGH
asynchronous inputs to each decade counter which
operates on the portion of the counter identified by the “1”
and “2” prefixes in the pin configuration. A HIGH level on
the nMR input overrides the clocks and sets the four
outputs LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
nCP
0
to nQ
0
nCP
1
to nQ
1
nCP
1
to nQ
2
nCP
1
to nQ
3
nMR to Q
n
maximum clock frequency nCP
0
, nCP
1
input capacitance
power dissipation capacitance per counter
C
L
= 15 pF; V
CC
= 5 V
14
15
23
15
16
66
3.5
20
18
19
26
19
18
61
3.5
21
ns
ns
ns
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
notes 1 and 2
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相關代理商/技術參數 |
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|---|---|
| 74HC390D | 功能描述:計數器 IC DUAL DECADE RIP CNTR RoHS:否 制造商:NXP Semiconductors 計數器類型:Binary Counters 邏輯系列:74LV 位數:10 計數法: 計數順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74HC390D,652 | 功能描述:計數器 IC DUAL DECADE RIP CNTR RoHS:否 制造商:NXP Semiconductors 計數器類型:Binary Counters 邏輯系列:74LV 位數:10 計數法: 計數順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74HC390D,653 | 功能描述:計數器 IC DUAL DECADE RIPPLE COUNTER RoHS:否 制造商:NXP Semiconductors 計數器類型:Binary Counters 邏輯系列:74LV 位數:10 計數法: 計數順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74HC390D | 制造商:NXP Semiconductors 功能描述:IC 74HC CMOS SMD 74HC390 SOIC16 |
| 74HC390D652 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP Semiconductors 功能描述:IC DECADE RIPPLE COUNTER DUAL SOIC-16 |
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