參數(shù)資料
型號(hào): 74HC238
廠商: NXP Semiconductors N.V.
英文描述: 3-to-8 line decoder/demultiplexer
中文描述: 3至8線路解碼器/解復(fù)用器
文件頁(yè)數(shù): 2/7頁(yè)
文件大?。?/td> 49K
代理商: 74HC238
December 1990
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
74HC/HCT238
FEATURES
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active HIGH mutually exclusive outputs
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT238 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT238 decoders accept three binary
weighted address inputs (A
0
, A
1
, A
2
) and when enabled,
provide 8 mutually exclusive active HIGH outputs
(Y
0
to Y
7
).
The “238” features three enable inputs: two active LOW
(E
1
and E
2
) and one active HIGH (E
3
). Every output will be
LOW unless E
1
and E
2
are LOW and E
3
is HIGH.
This multiple enable function allows easy parallel
expansion of the “238” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “238” ICs and one inverter.
The “238” can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data
input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their
appropriate active HIGH or LOW state.
The “238” is identical to the “138” but has non-inverting
outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
A
n
to Y
n
E
3
to Y
n
E
n
to Y
n
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
14
16
17
3.5
72
18
20
21
3.5
76
ns
ns
ns
pF
pF
C
I
C
PD
notes 1 and 2
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