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參數資料
| 型號： | 74HC1G66GW-G |
| 英文描述： | SC70/µDFN, Single/Dual Low-Voltage, Low-Power µP Reset Circuits |
| 中文描述： | SPST模擬開關 |
| 文件頁數： | 2/16頁 |
| 文件大?。?/td> | 78K |
| 代理商： | 74HC1G66GW-G |
2002 May 15
2
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74HC1G126; 74HCT1G126
FEATURES
Wide operating voltage from 2.0 to 6.0 V
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
Very small 5 pins package
Output capability: bus driver.
DESCRIPTION
The 74HC1G/HCT1G126 is a highspeed Si-gate CMOS
device.
The 74HC1G/HCT1G126 provides one non-inverting
buffer/line driver with 3-state output. The 3-state output is
controlled by the output enable input pin (OE). A LOW at
pin OE causes the output as assume a high-impedance
OFF-state.
The bus driver output currents are equal compared to the
74HC/HCT126.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= r
f
≤
6.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
For HC1G the conditions is V
I
= GND to V
CC
.
For HCT1G the conditions is V
I
= GND to V
CC
1.5 V.
2.
FUNCTION TABLE
See note 1.
Note
1.
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC1G
HCT1G
t
PHL
/t
PLH
C
I
C
PD
propagation delay A to Y
input capacitance
power dissipation capacitance
C
L
= 15 pF; V
CC
= 5 V
9
1.5
30
10
1.5
27
ns
pF
pF
notes 1 and 2
INPUTS
OUTPUT
OE
A
Y
H
H
L
L
H
X
L
H
Z
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