參數(shù)資料
型號(hào): 74HC1G00GW,165
廠商: NXP Semiconductors
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 0K
描述: IC 2-INPUT NAND GATE SC88A-5
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 10,000
系列: 74HC
邏輯類型: 與非門
電路數(shù): 1
輸入數(shù): 2
電源電壓: 2 V ~ 6 V
電流 - 靜態(tài)(最大值): 20µA
輸出電流高,低: 2.6mA,2.6mA
邏輯電平 - 低: 0.5 V ~ 1.8 V
邏輯電平 - 高: 1.5 V ~ 4.2 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 23ns @ 6V,50pF
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 5-TSSOP
封裝/外殼: 6-TSSOP(5 引線),SC-88A,SOT-353
包裝: 帶卷 (TR)
其它名稱: 74HC1G00GW-R
74HC1G00GW-R-ND
935245610165
74HC_HCT1G00
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 25 September 2013
5 of 12
NXP Semiconductors
74HC1G00; 74HCT1G00
2-input NAND gate
11. Dynamic characteristics
[1]
tpd is the same as tPLH and tPHL.
[2]
CPD is used to determine the dynamic power dissipation PD (W).
PD =CPD VCC2 fi + (CL VCC2 fo)where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
(C
L VCC
2
f
o) = sum of outputs
ICC
supply current
VI =VCC or GND; IO =0A;
VCC =5.5 V
--
10
-
20
A
I
CC
additional supply
current
per input; VCC = 4.5 V to 5.5 V;
VI =VCC 2.1 V; IO =0A
-
500
-
850
A
CI
input capacitance
- 1.5
-
pF
Table 7.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb =25 C.
Symbol
Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ
Max
Min
Max
Table 8.
Dynamic characteristics
GND = 0 V; tr = tf 6.0 ns; All typical values are measured at Tamb =25 C. For test circuit, see Figure 6
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ
Max
Min
Max
For type 74HC1G00
tpd
propagation delay A and B to Y; see Figure 5
VCC = 2.0 V; CL = 50 pF
-
25
115
-
135
ns
VCC = 4.5 V; CL =50pF
-
9
23
-
27
ns
VCC = 5.0 V; CL =15pF
-
7
-
ns
VCC = 6.0 V; CL =50pF
-
8
20
-
23
ns
CPD
power dissipation
capacitance
VI =GND to VCC
[2] -19
-
pF
For type 74HCT1G00
tpd
propagation delay A and B to Y; see Figure 5
VCC = 4.5 V; CL =50pF
-
12
24
-
27
ns
VCC = 5.0 V; CL =15pF
-
10
-
ns
CPD
power dissipation
capacitance
VI =GND to VCC 1.5 V
[2] -21
-
pF
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