參數(shù)資料
型號: 74HC191D,653
廠商: NXP Semiconductors
文件頁數(shù): 8/14頁
文件大?。?/td> 0K
描述: IC 4BIT BINAR UP/DN COUNT 16SOIC
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,500
系列: 74HC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向: 上,下
元件數(shù): 1
每個(gè)元件的位元數(shù): 4
計(jì)時(shí): 同步
計(jì)數(shù)速率: 39MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SO
包裝: 帶卷 (TR)
December 1990
3
Philips Semiconductors
Product specication
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf =6ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay CP to Qn
CL = 15 pF; VCC = 5 V
22
ns
fmax
maximum clock frequency
36
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per package
notes 1 and 2
31
33
pF
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