參數(shù)資料
型號: 74FR240SJ
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Octal Buffer/Line Driver with 3-STATE Outputs
中文描述: FR/FASTR SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20
封裝: 5.30 MM, EIAJ TYPE2, SOP-20
文件頁數(shù): 1/5頁
文件大?。?/td> 51K
代理商: 74FR240SJ
1999 Fairchild Semiconductor Corporation
DS010901
www.fairchildsemi.com
October 1991
Revised August 1999
7
74FR240
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The 74FR240 is an inverting octal buffer and line driver
designed to be employed as memory and address driver,
clock driver and bus oriented transmitter or receiver.
Features
I
3-STATE outputs drive bus lines or buffer memory
address registers
I
Outputs sink 64 mA and source 15 mA
I
Guaranteed pin-to-pin skew
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Order Number
74FR240SC
74FR240SJ
74FR240PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
OE
1
, OE
2
I
0
–I
7
O
0
–O
7
Output Enable Input (Active-LOW)
Inputs
Outputs
Inputs
Outputs
OE
1
I
n
(Pins 12, 14, 16, 18)
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE
2
I
n
(Pins 3, 5, 7, 9)
L
L
H
L
H
L
H
X
Z
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