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參數(shù)資料
| 型號： | 74FR1074SCX |
| 英文描述： | SC70/µDFN, Single/Dual Low-Voltage, Low-Power µP Reset Circuits |
| 中文描述： | 雙D型觸發(fā)器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 80K |
| 代理商： | 74FR1074SCX |
Philips Semiconductors
Product specification
74F74
Dual D-type flip-flop
1996 Mar 12
5
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
V
M
V
M
CPn
V
M
V
M
V
M
V
M
V
M
V
M
t
su
(H)
t
h
(H)
Dn
Qn
V
M
t
w
(H)
1/f
max
t
su
(L)
t
h
(L)
V
M
V
M
t
PLH
Qn
t
w
(L)
t
PHL
t
PHL
t
PLH
SF01276
Waveform 1.
time and hold times, and clock width, and maximum clock
frequency
Propagation delay for data to output, data setup
V
M
V
M
RDn
V
M
Qn
V
M
V
M
V
M
t
PLH
Qn
t
w
(L)
t
PHL
t
PHL
t
PLH
SDn
V
M
V
M
t
w
(L)
SF00050
Waveform 2.
set and reset pulse width
Propagation delay for set and reset to output,
SDn or RDn
V
M
V
M
t
rec
CPn
SF00051
Waveform 3.
Recovery time for set or reset to clock
TEST CIRCUIT AND WAVEFORMS
t
w
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
NEGATIVE
PULSE
POSITIVE
PULSE
t
w
AMP (V)
0V
0V
t
THL (
t
f
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLH
2.5ns
t
THL
2.5ns
1MHz
500ns
Input Pulse Definition
V
CC
family
74F
D.U.T.
PULSE
GENERATOR
R
L
C
L
R
T
V
IN
V
OUT
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
R
L
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
Termination resistance should be equal to Z
OUT
of
pulse generators.
C
L
=
R
T
=
t
THL (
t
f
)
t
TLH (
t
r
)
t
TLH (
t
r
)
AMP (V)
amplitude
3.0V
1.5V
V
M
SF00006
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F74 | Dual D-Type Positive Edge-Triggered Flip-Flop |
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| 74F74SJ | Dual D-Type Positive Edge-Triggered Flip-Flop |
| 74F74 | Dual D-Type Positive Edge-Triggered Flip-Flop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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