參數(shù)資料
型號(hào)： 74F74
廠商： Fairchild Semiconductor Corporation
英文描述： Dual D-Type Positive Edge-Triggered Flip-Flop
中文描述： 雙D型上升沿觸發(fā)器
文件頁(yè)數(shù)： 4/8頁(yè)
文件大?。?/td> 80K
代理商： 74F74
Philips Semiconductors
Product specification
74F74
Dual D-type flip-flop
1996 Mar 12
4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
MIN
TYP
2
MAX
V
OH
High level output voltage
High-level output voltage
= MIN V
V
CC
= MIN, V
IL
= MAX, V
IH
= MIN
= MAX V
= MAX
I
OH
±
10%V
CC
±
5%V
CC
±
10%V
CC
±
5%V
CC
2.5
V
2.7
3.4
V
V
OL
Low level output voltage
Low-level output voltage
= MIN V
V
CC
= MIN, V
IL
= MAX, V
IH
= MIN
= MAX V
= MAX
I
OL
0.30
0.50
V
0.30
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
-0.73
-1.2
V
I
I
Input current at maximum input
voltage
V
CC
= MAX, V
I
= 7.0V
100
μ
A
I
IH
High-level input current
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
20
μ
A
I
IL
Low-level input
current
Dn, CPn
-0.6
mA
SDn, RDn
-1.8
mA
I
OS
I
CC
Short-circuit output current
3
Supply current (total)
4
-60
-150
mA
11.5
16
mA
NOTES:
1
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2
All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3
Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4
Measure I
CC
with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25
°
C
C
L
= 50pF, R
L
= 500
V
CC
= +5.0V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
= 50pF, R
L
= 500
V
CC
= +5.0V
±
10%
T
amb
= –40
°
C to +85
°
C
C
L
= 50pF, R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
f
max
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency
Waveform 1
100
125
100
90
MHz
Propagation delay
CPn to Qn or Qn
Waveform 1
3.8
4.4
5.3
6.2
6.8
8.0
3.8
4.4
7.8
9.2
3.8
4.4
8.5
9.2
ns
Propagation delay
SDn, RDn
to Qn or Qn
Waveform 2
3.2
3.5
4.6
7.0
6.1
9.0
3.2
3.5
7.1
10.5
3.2
2.5
7.5
10.5
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25
°
C
C
L
= 50pF, R
L
= 500
V
CC
= +5.0V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
= 50pF, R
L
= 500
V
CC
= +5.0V
±
10%
T
amb
= –40
°
C to +85
°
C
C
L
= 50pF, R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
su
(H)
t
su
(L)
Setup time, high or low
Dn to CPn
Waveform 1
2.0
3.0
2.0
3.0
2.0
3.0
ns
t
h
(H)
t
h
(L)
Hold time, high or low
Dn to CPn
Waveform 1
1.0
1.0
1.0
1.0
1.0
1.0
ns
t
w
(H)
t
w
(L)
CPn pulse width,
high or low
Waveform 1
4.0
5.0
4.0
5.0
4.0
5.0
ns
t
w
(L)
SDn, RDn pulse width,
low
Waveform 2
4.0
4.0
4.0
ns
t
rec
Recovery time
SDn, RDn to CPn
Waveform 3
2.0
2.0
2.0
ns
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