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參數(shù)資料
| 型號(hào)： | 74F573DCX |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Octal D-Type Latch with TRI-STATE Outputs |
| 中文描述： | 八路D型鎖存器與三態(tài)輸出 |
| 文件頁(yè)數(shù)： | 6/14頁(yè) |
| 文件大小： | 107K |
| 代理商： | 74F573DCX |
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Philips Semiconductors
Product specification
74F573/74F574
Latch/flip-flop
1989 Oct 16
6
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
TYP
NO TAG
SYMBOL
PARAMETER
TEST CONDITIONS
NO TAG
MIN
MAX
UNIT
V
OH
High level output voltage
High-level output voltage
= MIN, V
= MAX,
V
CC
MIN, V
IL
MAX,
V
IH
= MIN, I
OH
= MAX
±
10%V
CC
±
5%V
CC
±
10%V
CC
±
5%V
CC
2.4
V
2.7
3.4
V
V
OL
Low level output voltage
Low-level output voltage
= MIN, V
= MAX,
V
CC
MIN, V
IL
MAX,
V
IH
= MIN, I
OL
= MAX
0.35
0.50
V
0.35
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
–0.73
–1.2
V
I
I
Input current at
maximum input voltage
V
CC
= MAX, V
I
= 7.0V
100
μ
A
I
IH
I
IL
High-level input current
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
20
μ
A
Low-level input current
–0.6
mA
I
OZH
Off-state output current,
High-level voltage applied
V
CC
= MAX, V
O
= 2.7V
50
μ
A
I
OZL
Off-state output current,
Low-level voltage applied
Short-circuit output current
NO TAG
V
CC
= MAX, V
O
= 0.5V
–50
μ
A
I
OS
V
CC
= MAX
–60
–150
mA
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
30
40
mA
74F573
V
CC
= MAX
35
50
mA
I
CC
Supply
current
(total)
40
60
mA
45
65
mA
74F574
V
CC
= MAX
50
70
mA
55
85
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
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