參數(shù)資料
型號: 74F569PC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 4-Bit Bidirectional Counter with 3-STATE Outputs
中文描述: F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP20
封裝: 0.300 INCH, MS-001, PLASTIC, DIP-20
文件頁數(shù): 2/14頁
文件大小: 130K
代理商: 74F569PC
Philips Semiconductors
Product specification
74F569
4-bit bidirectional binary synchronous counter (3-State)
2
1996 Jan 05
853–0376 16193
FEATURES
4-bit bidirectional counting – binary counter
Synchronous counting and loading
Look ahead carry capability for easy cascading
Preset capability for programmable operation
Master Reset (MR) overrides all other inputs
Synchronous Reset (SR) overrides counting and parallel loading
Clock Carry (CC) output to be used as a clock for flip-flops,
register and counters
3-State outputs for bus organized systems
DESCRIPTION
The 74F569 is a fully synchronous Up/Down binary counter. It
features preset capabilities for programmable operation, carry look
ahead for programmable operation, carry look ahead for easy
cascading, and U/D input to control the direction of counting. For
maximum flexibility there are both Synchronous and Master Reset
inputs as well as both Clocked Carry (CC) and Terminal Count (TC)
outputs. All state changes except Master Reset are initiated by
rising edge of the clock. A High signal on the Output Enable (OE)
input forces the output buffers into the high impedance state but
does not prevent counting, resetting or parallel loading.
PIN CONFIGURATION
20
19
18
17
16
15
14
13
8
7
6
5
4
3
2
1
VCC
TC
Q0
Q1
Q2
Q3
CET
PE
U/D
CP
D0
D1
D2
D3
CEP
GND
SF01072
MR
SR
CC
OE
12
11
10
9
TYPE
TYPICAL f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F569
115MHz
40mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
PKG.
DWG. #
20-pin plastic DIP
N74F569N
SOT146-1
20-pin plastic SO
N74F569D
SOT163-1
LOGIC SYMBOL
11
3
4
5
6
19
13
14
15
16
1
2
7
12
8
CP
CEP
CET
PE
D
0
D
1
D
2
D
3
Q
0
Q
1
Q
2
Q
3
TC
U/D
SF01056
9
MR
SR
17
OE
18
CC
V
=
GND =
Pin 20
Pin 10
LOGIC SYMBOL (IEEE/IEC)
M2[DOWN]
3
3,5D
EN10
SF01057
C5/1,4,7,8+/2,4,7,8–
M1[UP]
CTR DIV 10
19
1,7(CT=15)G9
2,7(CT=0)G9
Z6
G7
10
G8
M4[COUNT]
5CT=0
M3[LOAD]
CT=0
18
6,7,8,9
4
5
6
15
14
13
16
17
1
2
12
7
9
11
8
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