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參數(shù)資料
| 型號(hào)： | 74F50728 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Synchronizing cascaded dual positive edge-triggered D-type flip-flop |
| 中文描述： | 同步串聯(lián)雙上升沿觸發(fā)D型觸發(fā)器 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大小： | 89K |
| 代理商： | 74F50728 |
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
September 14, 1990
4
characteristics are greatly improved over using two separate flops
that are cascaded. The pin compatibility with the 74F74 allows for
plug–in retrofitting of previously designed systems.
Because the probability of failure of the 74F50728 is so remote, the
metastability characteristics of the part were empirically determined
based on the characteristics of its sister part, the 74F5074. The
table below shows the 74F5074 metastability characteristics.
Having determined the T
0
and
τ
of the flop, calculating the mean
time between failures (MTBF) for the 74F50728 is simple. It is,
however, somewhat different than calculating MTBF for a typical part
because data requires two clock pulses to transit from the input to
the output. Also, in this case a failure is considered of the output
beyond the normal propagation delay.
Suppose a designer wants to use the flop for synchronizing
asynchronous data that is arriving at 10MHz (as measured by a
frequency counter), and is using a clock frequency of 50MHz. He
simply plugs his number into the equation below:
MTBF = e
(t’/t)
/T
o
f
C
f
I
In this formula, f
C
is the frequency of the clock, f
I
is the average
input event frequency, and t’ is the period of the clock input (20
nanoseconds). In this situation the f
I
will be twice the data
frequency of 20 MHz because input events consist of both of low
and high data transitions. From Fig. 2 it is clear that the MTBF is
greater than 10
41
seconds. Using the above formula the actual
MTBF is 2.23 X 10
42
seconds or about 7 X 10
34
years.
TYPICAL VALUES FOR
τ
AND T
0
AT VARIOUS V
CC
S AND TEMPERATURES
T
amb
= 0
°
C
τ
T
0
T
amb
= 25
°
C
T
amb
= 70
°
C
τ
T
0
τ
T
0
V
CC
= 5.5V
125ps
1.0 X 10
9
sec
138ps
5.4 X 10
6
sec
160ps
1.7 X 10
5
sec
V
CC
= 5.0V
115ps
1.3 X 10
10
sec
135ps
9.8 X 10
6
sec
167ps
3.9 X 10
4
sec
V
CC
= 4.5V
115ps
3.4 X 10
13
sec
132ps
5.1 X 10
8
sec
175ps
7.3 X 10
4
sec
MEAN TIME BETWEEN FAILURES VERSUS DATA FREQUENCY AT VARIOUS CLOCK FREQUENCY
10
70
10
60
10
50
10
40
10
30
10
20
10
10
10
00
1K
100K
10M
Data frequency (Hz)
Mean time
between failures
(seconds)
Clock = 40MHz
Clock = 50MHz
Clock = 650MHz
Clock = 70MHz
Clock = 80MHz
Clock = 100MHz
1 billion years
NOTE: V
CC
= 5V, T
amb
= 25
°
C,
τ
=135ps, To = 9.8 X 10
8
sec
SF00610
Figure 2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F50729 | Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
| 74F5074 | Synchronizing dual D-type flip-flop/clock driver(同步雙D觸發(fā)器/時(shí)鐘驅(qū)動(dòng)器) |
| 74F51SCX | 2/2-input and 3/3-input AND-NOR Gate |
| 74F51SJX | 2/2-input and 3/3-input AND-NOR Gate |
| 74F51 | Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate(雙2位寬，2輸入，2方式 ，3輸入與或非門(mén)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F50729 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
| 74F5074 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Synchronizing dual D-type flip-flop/clock driver |
| 74F5074D | 制造商:SGS 功能描述:74F5074 SGS S1I2B 制造商:NXP Semiconductors 功能描述: |
| 74F5074N | 制造商:NXP Semiconductors 功能描述: |
| 74F51 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate |
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