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參數(shù)資料
| 型號(hào)： | 74F3893 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quad Futurebus backplane transceiver(四通道預(yù)置總線底板收發(fā)器) |
| 中文描述： | 四Futurebus背板收發(fā)器（四通道預(yù)置總線底板收發(fā)器） |
| 文件頁(yè)數(shù)： | 2/10頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | 74F3893 |
Philips Semiconductors
Product specification
74F3893
Quad Futurebus backplane transceiver
2
January 18, 1991
853-1397 01496
FEATURES
Quad backplane transceiver
Drives heavily loaded backplanes with equivalent load
impedances down to 10 ohms
Futurebus drivers sink 100mA
Reduced voltage swing (1 volt) produces less noise and
reduces power consumption
High speed operation enhances performance of backplane
buses and facilitates incident wave switching
Compatible with IEEE 896 and IEEE 1194.1 Futurebus
Standards
Built–in precision band–gap (BG) reference provides
accurate receiver thresholds and improved noise immunity
Glitch–free power up/power down operation on all outputs
Pin and function compatible with NSC DS3893
DESCRIPTION
The 74F3893 is a quad backplane transceivers and is
intended to be used in very high speed bus systems.
The 74F3893 interfaces to ‘Backplane Transceiver Logic’
(BTL). BTL features a reduced (1V to 2V) voltage swing for
lower power consumption and a series diode on the drivers
to reduce capacitive loading (< 5pF).
Incident wave switching is employed, therefore BTL
propagation delays are short. Although the voltage swing is
much less for BTL, so is its receiver threshold region,
therefore noise margins are excellent.
BTL offers low power consumption, low ground bounce, EMI
and crosstalk, low capacitive loading, superior noise margin
and low propagation delays. This results in a high
bandwidth, reliable backplane.
T
he 74F3893 has four TTL outputs (Rn) on the receiver
side with a common receiver enable input (RE). It has four
data inputs (Dn) which are also TTL. These data inputs are
NANDed with the data enable input (DE). The four I/O pins
(bus side) are futurebus compatible, sink a minimum of
100mA, and are designed to drive heavily loaded
backplanes with load impedances as low as 10 ohms. All
outputs are designed to be glitch–free during power up and
down.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPLY
CURRENT( TOTAL)
74F3893
3.0ns
55mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
N74F3893A
DESCRIPTION
PKG DWG #
20-pin PLCC
SOT380-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
20
μ
A/40
μ
A
20
μ
A/200
μ
A
20
μ
A/40
μ
A
100
μ
A/20
μ
A
D0 – D3
Data inputs
1.0/0.067
DE
Data enable input
1.0/0.33
RE
Receiver enable input
1.0/0.067
I/O0 – I/O3
Bus inputs
5.0/0.033
I/O0 – I/O3
Bus outputs
OC/166.7
OC/100mA
R0 – R7
Receiver outputs
150/40
3mA/24mA
Notes to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20
μ
A in the high state and 0.6mA in the low state.
OC= Open collector.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F38DC | Quad 2-input NAND Gate |
| 54F38LMQB | Quad 2-input NAND Gate |
| 74F38SCX | Quad 2-input NAND Gate |
| 74F38SJX | Quad 2-input NAND Gate |
| 74F38SC | Quad Two-Input NAND Buffer (Open Collector) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F38D | 制造商:NXP Semiconductors 功能描述:2INPUT NAND BUFFR(OPEN COLL.) |
| 74F38DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad 2-input NAND Gate |
| 74F38N | 制造商:NXP Semiconductors 功能描述:2INPUT NAND BUFFR(OPEN COLL.) |
| 74F38PC | 功能描述:邏輯門 Qd 2-Input NAND Buf RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74F38PC_Q | 功能描述:邏輯門 Qd 2-Input NAND Buf RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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