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參數(shù)資料
| 型號： | 74F377SJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal D-Type Flip-Flop with Clock Enable |
| 中文描述： | F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-20 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 143K |
| 代理商： | 74F377SJ |
TL/F/9525
5
May 1995
54F/74F377
Octal D Flip-Flop with Clock Enable
General Description
The ’F377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock tran-
sition, is transferred to the corresponding flip-flop’s Q out-
put. The CE input must be stable only one setup time prior
to the LOW-to-HIGH clock transition for predictable opera-
tion.
Features
Y
Ideal for addressable register applications
Y
Clock enable for address and data synchronization
applications
Y
Eight edge-triggered D flip-flops
Y
Buffered common clock
Y
See ’F273 for master reset version
Y
See ’F373 for transparent latch version
Y
See ’F374 for TRI-STATE
é
version
Y
Guaranteed 4000V minimum ESD protection
Commercial
Military
Package
Number
Package Description
74F377PC
N20A
20-Lead (0.300
×
Wide) Molded Dual-In-Line
54F377DM (QB)
J20A
20-Lead Ceramic Dual-In-Line
74F377SC (Note 1)
M20B
20-Lead (0.300
×
Wide) Molded Small Outline, JEDEC
20-Lead (0.300
×
Wide) Molded Small Outline, EIAJ
74F377SJ (Note 1)
M20D
54F377FM (QB)
W20A
20-Lead Cerpack
54F377LM (QB)
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1:
Devices also available in 13
×
reel. Use suffix
e
SCX and SJX.
Logic Symbols
TL/F/9525–1
IEEE/IEC
TL/F/9525–4
TRI-STATE
é
is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
RRD-B30M75/Printed in U. S. A.
相關PDF資料 |
PDF描述 |
|---|---|
| 74F379 | Quad Parallel Register with Enable |
| 74F379SC | Quad Parallel Register with Enable |
| 74F379SJ | Quad Parallel Register with Enable |
| 74F379PC | Quad Parallel Register with Enable |
| 74F379 | Quad Parallel Register with Enable |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74F377SJ_Q | 功能描述:觸發(fā)器 Qd 2-Input NAND Buff RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74F377SJX | 功能描述:觸發(fā)器 Octal Flip-Flop Clock Enable D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74F378 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Parallel D-Type Register with Enable |
| 74F378 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F378D | 制造商:NXP Semiconductors 功能描述:F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16 |
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