參數(shù)資料
型號: 74F373
廠商: Fairchild Semiconductor Corporation
英文描述: Octal Transparent Latch with 3-STATE Outputs
中文描述: 八路透明鎖存器與三態(tài)輸出
文件頁數(shù): 2/8頁
文件大?。?/td> 174K
代理商: 74F373
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I
IH
/I
IL
Output I
OH
/I
OL
HIGH/LOW
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
TRI-STATE Latch Outputs
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
b
3 mA/24 mA (20 mA)
Functional Description
The ’F373 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D in-
puts a setup time preceding the HIGH-to-LOW transition of
LE. The TRI-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Truth Table
Inputs
Output
LE
OE
D
n
O
n
H
H
L
X
L
L
L
H
H
L
X
X
H
L
O
n
(no change)
Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance State
Logic Diagram
TL/F/9523–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
相關(guān)PDF資料
PDF描述
74F373PC Octal Transparent Latch with 3-STATE Outputs
74F373SJ Octal Transparent Latch with 3-STATE Outputs
74F373SC Octal Transparent Latch with 3-STATE Outputs
74F374 Octal D-Type Flip-Flop with TRI-STATE Outputs(帶時鐘使能端八路D觸發(fā)器)
74F377 Octal D Flip-Flop with Clock Enable(帶時鐘使能端八路D觸發(fā)器)
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