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參數(shù)資料
| 型號： | 74F32 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Quad 2-Input OR Gate |
| 中文描述： | 四2輸入或門 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 69K |
| 代理商： | 74F32 |
Philips Semiconductors
Product specification
74F32
Quad 2-input OR gate
2
October 4, 1990
853 0333 00624
FEATURE
Industrial temperature range available (–40
°
C to +85
°
C)
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F32
4.1ns
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
V
CC
D2b
D2a
Q2
Q3
D3b
D3a
D0a
D0b
Q1
Q0
D1a
D1b
SF00038
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%, T
amb
= 0
°
C to +70
°
C
N74F32N
INDUSTRIAL RANGE
V
CC
= 5V
±
10%, T
amb
= –40
°
C to +85
°
C
I74F32N
PKG DWG #
14-pin plastic DIP
SOT27-1
14-pin plastic SO
N74F32D
I74F32D
SOT108–1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
Dna, Dnb
Data inputs
1.0/1.0
20
μ
A/0.6mA
Qn
Data output
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
μ
A in the high state and 0.6mA in the low state.
LOGIC DIAGRAM
D0a
D0b
D1a
D1b
D2a
D2b
Q0
D3a
D3b
Q1
Q2
Q3
V
= Pin 14
GND = Pin 7
3
6
8
11
1
2
4
5
9
10
12
13
SF00039
FUNCTION TABLE
INPUTS
OUTPUT
Dna
Dnb
Qn
L
L
L
L
H
H
H
L
H
H
H
H
NOTES:
1
H = High voltage level
2
L = Low voltage level
LOGIC SYMBOL
D0a D0bD1a
D2a D2b D3a D3b
D1b
Q0 Q1 Q2 Q3
3
6
8
11
1
2
4
5
9
10 12 13
V
= Pin 14
GND = Pin 7
SF00040
IEC/IEEE SYMBOL
1
2
4
5
9
10
12
13
3
6
8
11
SF00041
1
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