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Philips Semiconductors
Application note
AN214
74F extended octal-plus family applications
June 1988
7
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
OEAB OEBA CPAB CPBA SAB SBA
OEAB OEBA CPAB CPBA SAB SBA
OEAB OEBA CPAB CPBA SAB SBA
OEAB OEBA CPAB CPBA SAB SBA
BUS A
BUS A
BUS A
BUS A
BUS B
BUS B
BUS B
BUS B
SF00409
L
L
X
X
X
L
H
H
X
X
L
X
X
H
↑
X
X
X
L
X
X
↑
↑
X
X
L
H
↑
X
X
H
L
H or L H or L
H
H
Figure 8. 74F651A–654A Registered Transceivers Storage Options (74F646A–649A not shown)
Table 2. Parity Bus Family versus the Competition
PART NUMBER
DESCRIPTION
TOTAL #
OF PINS
t
*
IN to OUT
t
*
IN to PARITY
I
CCmax
**
POWER
PINS
BROADSIDE
DESIGN
74F455/F456
vs.
74F240/F244 + 74F280
Octal Parity Buffer
24
7.5ns
16.0ns
110mA
Center
Yes
38
7.5ns
14.5ns
125mA
Corner
No
74F655A/F656A
vs.
74F240/F244 + 74F280
Octal Parity Buffer
24
7.5ns
16.0ns
110mA
Corner
Yes
38
7.5ns
14.5ns
125mA
Corner
No
74F657
vs.
Octal Parity Transceiver
24
7.5ns
16.0ns
110mA
Center
Yes
74F240/F245 + 74F280
+ 1 AND gate
NOTES:
*
Propagation delays of DATA IN-to-DATA OUT and IN-to-PARITY OUT, T
amb
= 0
°
C to 70
°
C, V
CC
= +5.0V
±
10%,
Output Load = C
= 50pF, and R
= 500
.
** Worst case power, T
amb
= 0
°
C to 70
°
C, V
CC
= +5.0V
±
10%, Output Load = C
L
= 50pF, and R
L
= 500
.
38
8.0ns
14.5ns
125mA
Corner
No
74F821–74F863 Series
The 74F821 through 74F863 Series of Octal 9-bit and 10-bit Buffers,
Latch Buffers, Register Buffers and Transceivers are standardized
around the AMD 298XX series with one significant difference—the
Philips Semiconductors “Light-Load” NPN input offers a 50:1
reduction in input loading (1000
μ
A vs. 20
μ
A). This series illustrates
the standardized on 24-pin/300mil-wide Slim-DIP packages,
“broadside” input/output pinouts and control function pins. All
74F8XX 3-State outputs are guaranteed to source/sink
–15mA/64mA, except for the 74F84X Latched Buffers, which are
specified at –15mA/48mA.
The logic diagram and pin configurations of the 74F828
Non-Inverting 10-bit Buffer (Figure 1) and the 74F821–826 and
74F841–846 Registered/Latched Buffers (Figure 4) are excellent
illustrations of the standardized pin configuration illustrating
“broadside” chip design.
Figure 5 shows the pinouts of the 74F827/828 buffers and
74F861–864 Transceivers. There currently are no 9-bit buffer
offerings in this series.
Registered Transceiver Series
the 74F646A–649A and 74F651A–654A Octal Dual-Registered
Transceivers offer a “Light-Load” combination of a 74F245 type
transceiver with two 74F373/374 type octal registers within a 24-pin
Slim-DIP broadside input/output package. This series offers a
significant 6:1 package count reduction advantage over older
technologies.
Figure 6 shows the 74F646A and 74F651A Transceivers Simplified
Block Diagrams, and this series’ pin configurations are depicted in
Figure 7. Figure 8 graphically illustrates four optional storage and
transfer modes of the 74F651A Octal, Non-Inverting, 3-State,
Dual-Registered Transceiver. The 74F654A will be used to explain
the operation of the entire series. The 74F646A/648A (3-State,
INV/NINV) and the 74F647/649 (O.C., INV/NINV) Octal
Dual-Registered Transceivers offer optional signal direction control
logic and output enable to the 74F651A–654A series.
This series allows you to store or real-time transfer data in either
direction through the transceiver function. Data at the A
N
port can be
stored in either the A
N
port register or the B
N
register and, then, can