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參數(shù)資料
| 型號： | 74F27SJX |
| 英文描述： | Triple 3-input NOR Gate |
| 中文描述： | 三3輸入或非門 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 70K |
| 代理商： | 74F27SJX |
Philips Semiconductors
Product specification
74F27
Triple 3-input NOR gate
2
February 5, 1991
853 0049 01638
FEATURE
Industrial temperature range available (–40
°
C to +85
°
C)
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F27
3.0ns
6.5mA
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
V
CC
D2b
D2a
Q2
D2c
D0c
Q0
D0a
D0b
Q1
D1a
D1b
D1c
SF00033
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%, T
amb
= 0
°
C to +70
°
C
N74F27N
INDUSTRIAL RANGE
V
CC
= 5V
±
10%, T
amb
= –40
°
C to +85
°
C
I74F27N
PKG DWG #
14-pin plastic DIP
SOT27-1
14-pin plastic SO
N74F27D
I74F27D
SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
20
μ
A/0.6mA
Dna, Dnb, Dnc
Data inputs
1.0/1.0
Qn
Data output
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
μ
A in the high state and 0.6mA in the low state.
LOGIC DIAGRAM
V
= Pin 14
GND = Pin 7
SF00034
Q0
Q1
Q2
12
6
8
1
2
13
3
4
5
9
10
11
D0a
D0b
D0c
D1a
D1b
D1c
D2a
D2b
D2c
FUNCTION TABLE
INPUTS
OUTPUT
Dna
Dnb
Dnc
Qn
L
L
L
H
X
X
H
L
X
H
X
L
H
X
X
L
NOTES:
H = High voltage level
L
= Low voltage level
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