參數(shù)資料
型號: 74F244SJX
英文描述: Dual 4-Bit Non-Inverting Buffer/Driver
中文描述: 雙4位非反向緩沖器/驅(qū)動器
文件頁數(shù): 6/12頁
文件大?。?/td> 147K
代理商: 74F244SJX
Philips Semiconductors
Product specification
74F240/74F240A/
74F241/74F241A
Buffers
6
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
TYP
2
UNIT
CONDITIONS
1
MIN
MAX
V
CC
= MIN,
I
OH
= –3mA
±
10%V
C
±
5%V
CC
2.4
V
V
OH
High-level output voltage
V
IL
= MAX,
2.7
3.4
V
V
IH
= MIN
I
OH
=
–15mA
±
10%V
C
±
5%V
CC
2.0
V
2.0
V
V
OL
Low-level output voltage
V
CC
= MIN,
V
IL
= MAX,
V
IH
= MIN,
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
I
OL
= MAX
±
10%V
C
C
±
5%V
CC
0.50
V
0.42
0.50
V
V
IK
I
I
I
IH
Input clamp voltage
–0.73
-1.2
V
μ
A
μ
A
Input current at maximum input voltage
100
High–level input current
20
74F240 all inputs
–1.0
mA
74F240A all inputs
–100
μ
A
I
IL
Low–level input current
74F241 OEa, OEb
V
CC
= MAX, V
I
= 0.5V
–1.0
mA
74F241 Ian, Ibn
–1.6
mA
74F241A all inputs
–40
μ
A
I
OZH
Off–state output current,
high–level voltage applied
V
CC
= MAX, V
O
= 2.7V
50
μ
A
I
OZL
Off–state output current,
low–level voltage applied
V
CC
= MAX, V
O
= 0.5V
–50
μ
A
I
OS
Short–circuit output current
3
V
CC
= MAX
-100
-225
mA
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
12
18
mA
74F240
50
70
mA
V
CC
= MAX
35
45
mA
28
37
mA
74F240A
58
75
mA
I
CC
Supply current (total)
34
50
mA
40
60
mA
74F241
60
90
mA
V
CC
= MAX
65
90
mA
20
30
mA
74F241A
49
65
mA
26
40
mA
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
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