參數(shù)資料
型號: 74F195A
廠商: NXP Semiconductors N.V.
英文描述: 4-bit parallel-access shift register(4位并行訪問移位寄存器)
中文描述: 4位并行存取移位寄存器(4位并行訪問移位寄存器)
文件頁數(shù): 6/10頁
文件大?。?/td> 74K
代理商: 74F195A
Philips Semiconductors
Product specification
74F195A
4-bit parallel-access shift register
1996 Mar 12
6
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5V
T
= +25
°
C
C
L
= 50pF, R
L
= 500
V
CC
= +5V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
t
S
(H)
t
S
(L)
t
h
(H)
t
h
(L)
t
S
(H)
t
S
(L)
t
h
(H)
t
h
(L)
Setup time, High or Low
J, K and Dn to CP
Waveform 3
2.5
2.5
2.5
2.5
ns
Hold time, High or Low
J, K and Dn to CP
Waveform 3
0.0
1.0
0.0
1.0
ns
Setup time, High or Low
PE to CP
Waveform 4
2.0
2.5
2.0
2.5
ns
Hold time, High or Low
PE to CP
Waveform 4
0.0
0.0
0.0
0.0
ns
t
W
(H)
CP Pulse width
High
Waveform
NO TAG
4.5
4.5
ns
t
W
(L)
MR Pulse width
Low
Waveform 2
4.5
4.5
ns
t
REC
Recovery time
MR to CP
Waveform 2
2.5
3.0
ns
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
t
PHL
t
PLH
CP
V
M
V
M
V
M
t
w
(H)
1/f
max
V
M
V
M
t
PLH
Q3
V
M
V
M
Qn
t
PHL
SF00761
Waveform 1.
Clock Pulse Width, and Maximum Clock Frequency
Propagation Delay, Clock Input to Output,
t
h
(H)
t
s
(H)
CP
SF00763
V
M
V
M
V
M
V
M
V
M
V
M
t
h
(L)
t
s
(L)
J, K,
Dn
Waveform 2. Data Setup and Hold Times
CP
V
M
V
M
V
M
V
M
t
PHL
t
rec
MR
Qn
t
w
(L)
V
M
Q3
t
PLH
SF00762
Waveform 3. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Clock Recovery Time
CP
V
M
V
M
V
M
V
M
V
M
V
M
PE
Qn
t
s
(H)
SF00764
t
h
t
s
(L)
RESPONSE
Qn=Qn–1
Qn=Dn
SERIAL-SHIFT RIGHT
PARALLEL LOAD
t
h
Waveform 4. Setup and Hold Times, Parallel Enable to Clock
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