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參數(shù)資料
| 型號： | 74C86 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Quad 2-Input EXCLUSIVE-OR Gate |
| 中文描述： | 四2輸入異或門 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 54K |
| 代理商： | 74C86 |
October 1987
Revised January 1999
M
1999 Fairchild Semiconductor Corporation
DS005887.prf
www.fairchildsemi.com
MM74C86
Quad 2-Input EXCLUSIVE-OR Gate
General Description
The MM74C86 employs complementary MOS (CMOS)
transistors to achieve wide power supply operating range,
low power consumption and high noise margin these gates
provide basic functions used in the implementation of digi-
tal integrated circuit systems. The N- and P-channel
enhancement mode transistors provide a symmetrical cir-
cuit with output swing essentially equal to the supply volt-
age. No DC power other than that caused by leakage
current is consumed during static condition. All inputs are
protected from damage due to static discharge by diode
clamps to V
CC
and GND.
Features
I
Wide supply voltage range:
I
Guaranteed noise margin:
I
High noise immunity:
3.0V to 15V
1.0V
0.45 V
CC
(typ.)
I
Low power:
Fan out of 2 driving 74L
I
Low power consumption:
I
The MM74C86 follows the MM74LS86 Pinout
TTL compatibility:
10 nW/package (typ.)
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Truth Table
H
=
HIGH Level
L
=
LOW Level
Order Number
MM74C86M
MM74C86N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Inputs
Output
Y
L
H
H
L
A
L
L
H
H
B
L
H
L
H
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