參數(shù)資料
型號(hào): 74AVCH16244DGG,118
廠商: NXP Semiconductors
文件頁(yè)數(shù): 10/16頁(yè)
文件大?。?/td> 0K
描述: IC BUFF DVR TRI-ST 16BIT 48TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,000
系列: 74AVCH
邏輯類型: 緩沖器/線路驅(qū)動(dòng)器,非反相
元件數(shù): 4
每個(gè)元件的位元數(shù): 4
輸出電流高,低: 12mA,12mA
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 帶卷 (TR)
其它名稱: 935266778118
2000 Mar 07
3
Philips Semiconductors
Product Specication
16-bit buffer/line driver; 3.6 V tolerant;
3-state
74AVCH16244
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
∑ (CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high impedance OFF-state.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
tPHL/tPLH
propagation delay nAn to nYn
VCC = 1.2 V
5.2
ns
VCC = 1.5 V
2.9
ns
VCC = 1.8 V
2.1
ns
VCC = 2.5 V
1.5
ns
VCC = 3.3 V
1.3
ns
CI
input capacitance
5.0
pF
CPD
power dissipation capacitance per buffer
notes 1 and 2
outputs enabled
34
pF
outputs disabled
1
pF
INPUTS
OUTPUTS
nOE
nAn
nYn
LL
L
LH
H
HX
Z
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