- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8077 > 74ALVCH16646DGG:11 (NXP Semiconductors)IC TRANSCVR 16BIT N-INV 56TSSOP PDF資料下載
參數(shù)資料
| 型號： | 74ALVCH16646DGG:11 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSCVR 16BIT N-INV 56TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標準包裝： | 2,000 |
| 系列： | 74ALVCH |
| 邏輯類型： | 寄存收發(fā)器，非反相 |
| 元件數(shù)： | 2 |
| 每個元件的位元數(shù)： | 8 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 74ALVCH16646DG-T 74ALVCH16646DG-T-ND 935262421118 |
Philips Semiconductors
Product specification
74ALVCH16646
16-bit bus transceiver/register (3-State)
2
1998 Sep 03
853-2116 19959
FEATURES
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTETM flow-through pin-out architecture
Low inductance, multiple V
CC and ground pins for minimum noise
and ground bounce
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
Output drive capability 50 transmission lines @ 85°C
All inputs have bushold circuitry
DESCRIPTION
The 74ALVCH16646 consists of 16 non-inverting bus transceiver
circuits with 3-State outputs, D-type flip-flops and control circuitry
arranged for multiplexed transmission of data directly from the
internal registers. Data on the ‘A’ or ‘B’ bus will be clocked in the
internal registers, as the appropriate clock (CPAB or CPBA) goes to a
HIGH logic level. Output enable (OE) and direction (DIR) inputs are
provided to control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in either the
‘A’ or ‘B’ register, or in both. The select source inputs (SAB and SBA)
can multiplex stored and real-time (transparent mode) data. The
direction (DIR) input determines which bus will receive data when
OE is active (LOW). In the isolation mode (OE = HIGH), ‘A’ data
may be stored in the ‘B’ register and/or ‘B’ data may be stored in the
‘A’ register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, ‘A’ or ‘B’ may be driven at a time.
To ensure the high impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1DIR
1CPAB
1SAB
GND
1A0
1A1
VCC
1A3
1A4
GND
1A5
1A6
1A7
2A0
1A2
2A1
2A2
GND
2A3
2A4
2B4
2B3
GND
2B2
2B1
2B0
1B7
1B6
1B5
GND
1B4
1B3
1B2
VCC
1B1
1B0
GND
1SBA
1CPBA
1OE
21
22
23
24
33
34
35
36
2A5
VCC
2A6
2A7
2B7
2B6
VCC
2B5
25
26
27
28
29
30
31
32
GND
2SAB
2CPAB
2DIR
2OE
2CPBA
2SBA
GND
SY00011
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
nAx to nBx
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
2.6
2.7
ns
CI
Input capacitance
3.0
pF
C
Power dissipation capacitance per channel
V = GND to VCC1
Outputs enabled
36
pF
CPD
Power dissipation capacitance per channel
VI = GND to VCC1
Outputs disabled
4
pF
Fmax
Maximum clock frequency
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
300
320
MHz
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic TSSOP Type II
–40
°C to +85°C
74ALVCH16646 DGG
ACH16646 DGG
SOT364-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ALVCH16543DGG,11 | IC TRANSCVR TRI-ST 16BIT 56SSOP |
| IDT74FCT3244SOG8 | IC BUFF/DVR DUAL N-INV 20SOIC |
| IDT74FCT3244PYG8 | IC BUFF/DVR DUAL N-INV 20SSOP |
| OSTH407505C | CONN PLUG HEADER 7PS 5.08MM |
| IDT74FCT3244ASOG8 | IC BUFF/DVR DUAL N-INV 20SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVCH16646DGGRE4 | 功能描述:總線收發(fā)器 16B Bus Trnscvr/Reg RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVCH16646DGGRG4 | 功能描述:總線收發(fā)器 16B Bus Xceiver And Register RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVCH16646DGGS | 功能描述:IC TXRX/REGISTER 16BIT 56TSSOP 制造商:nexperia usa inc. 系列:74ALVCH 包裝:管件 零件狀態(tài):在售 邏輯類型:收發(fā)器，非反相 元件數(shù):2 每元件位數(shù):8 輸入類型:- 輸出類型:推挽式 電流 - 輸出高，低:24mA，24mA 電壓 - 電源:2.3 V ~ 2.7 V，3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商器件封裝:56-TSSOP 標準包裝:35 |
| 74ALVCH16646DGG-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 8-bit Bus Transceiver |
| 74ALVCH16646DGGY | 功能描述:Transceiver, Non-Inverting 2 Element 8 Bit per Element Push-Pull Output 56-TSSOP 制造商:nxp semiconductors 系列:74ALVCH 包裝:帶卷（TR） 零件狀態(tài):有效 邏輯類型:收發(fā)器，非反相 元件數(shù):2 每元件位數(shù):8 輸入類型:- 輸出類型:推挽式 電流 - 輸出高，低:24mA，24mA 電壓 - 電源:2.3 V ~ 2.7 V，3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商器件封裝:56-TSSOP 標準包裝:2,000 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。