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| 型號： | 74ALVC16500MTDX |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 18-Bit Bus Transceiver |
| 中文描述： | 18位總線收發(fā)器 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 85K |
| 代理商： | 74ALVC16500MTDX |
2001 Fairchild Semiconductor Corporation
DS500684
www.fairchildsemi.com
October 2001
Revised October 2001
7
74ALVC16500
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16500 is an 18-bit universal bus transceiver
which combines D-type latches and D-type flip-flops to
allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. When OEAB is HIGH, the outputs are
active. When OEAB is LOW, the outputs are in a high-
impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
The ALVC16500 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVC16500 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I
1.65V–3.6V V
CC
supply operation
I
3.6V tolerant inputs and outputs
I
t
PD
(A to B, B to A)
3.4 ns max for 3.0V to 3.6V V
CC
4.0 ns max for 2.3V to 2.7V V
CC
7.0 ns max for 1.65V to 1.95V V
CC
I
Power-off high impedance inputs and outputs
I
Supports live insertion/withdrawal (Note 1)
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OEBA should be tied to V
CC
through a pull-up resistor and OEAB
should be tied to GND through a pull-down resistors; the minimum value of
the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Devices also available on Tape and Reel. Specify by appending the suffix letter
“
X
”
to the ordering code.
Order Number
74ALVC16500MTD
Package Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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| 74ALVC16501MTD | Triple 3-Input Positive-AND Gates 14-SO -40 to 85 |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 74ALVC16501 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs |
| 74ALVC16501DGG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit Bus Transceiver |
| 74ALVC16501DL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit Bus Transceiver |
| 74ALVC16501MTD | 功能描述:總線收發(fā)器 18-Bit Universal Bus RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVC16501MTD_Q | 功能描述:總線收發(fā)器 18-Bit Universal Bus RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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