參數(shù)資料
型號(hào): 74ALVC162839TX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: BUFFER/FLIP-FLOP|AVC/ALVC-CMOS|TSSOP|56PIN|PLASTIC
中文描述: ALVC/VCX/A SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO56
封裝: 6.10 MM, MO-153, TSSOP-56
文件頁數(shù): 1/6頁
文件大小: 83K
代理商: 74ALVC162839TX
2001 Fairchild Semiconductor Corporation
DS500712
www.fairchildsemi.com
November 2001
Revised November 2001
7
R
74ALVC162839
Low Voltage 20-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs/Outputs
and 26
Series Resistors in the Outputs
General Description
The ALVC162839 contains twenty non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CLK) sig-
nals. The device operates in a 20-bit word wide mode. All
outputs can be placed into 3-STATE through use of the OE
pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
The 74ALVC162839 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC162839 is also designed with 26
series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVC162839 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I
Compatible with PC100 and PC133 DIMM module
specifications
I
1.65V–3.6V V
CC
supply operation
I
3.6V tolerant inputs and outputs
I
26
series resistors in the outputs
I
t
PD
(CLK to O
n
)
4.6 ns max for 3.0V to 3.6V V
CC
6.3 ns max for 2.3V to 2.7V V
CC
9.8 ns max for 1.65V to 1.95V V
CC
I
Power-off high impedance inputs and outputs
I
Supports live insertion and withdrawal (Note 1)
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter
X
to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
74ALVC162839T
Package Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
Output Enable Input (Active LOW)
I
0
I
19
O
0
O
19
CLK
Inputs
Outputs
Clock Input
REGE
Register Enable Input
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74ALVC163245TX 功能描述:總線收發(fā)器 Translating Transcvr LV 16Bit Dual Supply RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ALVC16334 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit registered driver with inverted register enable 3-State