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參數(shù)資料
| 型號： | 74ALS573 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS |
| 中文描述： | 八路?- 3型透明鎖存態(tài)輸出 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 134K |
| 代理商： | 74ALS573 |
SN54ALS573C, SN54AS573A, SN74ALS573C, SN74AS573A
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SDAS048D – DECEMBER 1989 – REVISED JANUARY 1995
Copyright
1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3-State Buffer-Type Outputs Drive Bus
Lines Directly
Bus-Structured Pinout
True Logic Outputs
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), Standard Plastic (N) and
Ceramic (J) 300-mil DIPs, and Ceramic Flat
(W) Packages
description
These octal D-type transparent latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing
buffer
bidirectional bus drivers, and working registers.
registers,
I/O
ports,
While the latch-enable (LE) input is high, outputs
(Q) respond to the data (D) inputs. When LE is low,
the outputs are latched to retain the data that was
set up.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or a high-impedance state. In
the high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE does not affect internal operation of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
The SN54ALS573C and SN54AS573A are characterized for operation over the full military temperature range
of –55
°
C to 125
°
C. The SN74ALS573C and SN74AS573A are characterized for operation from 0
°
C to 70
°
C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
D
H
H
L
H
L
L
L
L
X
Q0
Z
H
X
X
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
SN54ALS573C, SN54AS573A . . . J OR W PACKAGE
SN74ALS573C, SN74AS573A . . . DW OR N PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
SN54ALS573C, SN54AS573A . . . FK PACKAGE
(TOP VIEW)
2
1
O
8
7
1
8
G
L
V
C
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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相關(guān)代理商/技術(shù)參數(shù) |
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| 74ALS573B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Latch flip-flop |
| 74ALS573BD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Latch flip-flop |
| 74ALS573BDB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Latch flip-flop |
| 74ALS573BDW | 制造商:MAJOR 功能描述: |
| 74ALS573BN | 制造商:NXP Semiconductors 功能描述: |
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