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參數(shù)資料
| 型號(hào)： | 74AHCT273PW,118 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC OCT D FF POS-EDG TRIG 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 74AHCT |
| 功能： | 主復(fù)位 |
| 類型： | D 型總線 |
| 輸出類型： | 非反相 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 8 |
| 頻率 - 時(shí)鐘： | 50MHz |
| 延遲時(shí)間 - 傳輸： | 5.8ns |
| 觸發(fā)器類型： | 正邊沿 |
| 輸出電流高，低： | 8mA，8mA |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 568-7613-6 |
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1.
General description
The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specied in compliance with JEDEC standard
No. 7-A.
The 74AHC273; 74AHCT273 has eight edge-triggered, D-type ip-ops with individual D
inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs, load and reset (clear) all ip-ops
simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the ip-op.
All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR
input.
The device is useful for applications where only the true output is required and the clock
and master reset are common to all storage elements.
2.
Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Inputs accept voltages higher than VCC
I Ideal buffer for MOS microcontroller or memory
I Common clock and master reset
I Related product versions:
N 74AHC377; 74AHCT377 for clock enable version
N 74AHC373; 74AHCT373 for transparent latch version
N 74AHC374; 74AHCT374 for 3-state version
I Input levels:
N For 74AHC273: CMOS level
N For 74AHCT273: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specied from 40 °C to +85 °C and from 40 °C to +125 °C
74AHC273; 74AHCT273
Octal D-type ip-op with reset; positive-edge trigger
Rev. 03 — 13 May 2008
Product data sheet
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74AHCT273PW-Q100J | 制造商:NXP Semiconductors 功能描述:Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin TSSOP T/R 制造商:NXP Semiconductors 功能描述:74AHCT273PW-Q100/TSSOP20/REEL1 - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC FLIP-FLOP OCTAL D 20TSSOP |
| 74AHCT273PW-T | 功能描述:觸發(fā)器 OCT D F/FW/RESET POS EDGE TR RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74AHCT2G | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 2-input OR gate |
| 74AHCT2G00 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 2-input NAND gate |
| 74AHCT2G00DC | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 2-input NAND gate |
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