參數(shù)資料
型號(hào)： 74AHC126PWDH
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： Quad buffer/line driver; 3-state
中文描述： AHC SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
封裝： 4.40 MM, PLASTIC, SOT-402-1, TSSOP-14
文件頁(yè)數(shù)： 2/16頁(yè)
文件大?。?/td> 78K
代理商： 74AHC126PWDH
1999 Sep 29
2
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger
actions
Inputsacceptsvoltageshigherthan
V
CC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125
°
C.
DESCRIPTION
The 74AHC/AHCT126 are
high-speed Si-gate CMOS devices
and are pin compatible with low
power Schottky TTL (LSTTL). They
are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT126 are four
non-inverting buffer/line drivers with
3-state outputs. The 3-state outputs
(nY) are controlled by the output
enable input (nOE) A LOW at nOE
causes the outputs to assume a
HIGH-impedance OFF state.
The ‘126’ is identical to the ‘125’ but
has active HIGH enable inputs.
FUNCTION TABLE
See note 1.
Note
1.
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF state.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
PINNING
INPUTS
OUTPUT
nOE
nA
nY
H
H
L
L
H
X
L
H
Z
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
nA to nY
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 15 pF;
V
CC
= 5 V
V
I
= V
CC
or GND
3.3
3.0
ns
C
I
C
O
C
PD
3.0
4.0
10
3.0
4.0
12
pF
pF
pF
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
PIN
SYMBOL
DESCRIPTION
1, 4, 10 and 13
2, 5, 9 and 12
3, 6, 8 and 11
7
14
1OE to 4OE
1A to 4A
1Y to 4Y
GND
V
CC
output enable inputs (active HIGH)
data inputs
data outputs
ground (0 V)
DC supply voltage
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