參數(shù)資料
型號(hào): 74AC299MTR
廠商: 意法半導(dǎo)體
元件分類: 通用總線功能
英文描述: 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR
中文描述: 8位皮普移位寄存器帶異步清零
文件頁數(shù): 2/13頁
文件大小: 465K
代理商: 74AC299MTR
74AC299
2/13
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
* When one or both controls are high, the eight input/output terminals are the high impedance state: howewer sequential operation or cleaning
of the register is not affected.
Z : High Impedance
Qn0 : The level of An before the indicated steady state input conditions were established.
Qnn : The level of Qn before the most recent active transition indicated by OR
a, h : The level of the steadystate inputs A, H, respectively.
X : Don’t Care
PIN No
SYMBOL
NAME AND FUNCTION
1, 19
2, 3
S0, S1
G1, G2
A/QA to H/QH
QA’ to QH’
CLEAR
SR
CLOCK
SL
GND
V
CC
Mode Select Inputs
3-State Output Enable Inputs (Active LOW)
Parallel Data Inputs or 3-State Parallel Outputs (Bus Driver)
Serial Outputs (Standard Output)
Asynchronous Master Reset Input (Active LOW)
Serial Data Shift Right Input
Clock Input (LOW to HIGH, Edge-triggered)
Serial Data Shift Left Input
Ground (0V)
Positive Supply Voltage
7, 13, 6, 14, 5, 15, 4, 16
8, 17
9
11
12
18
10
20
MODE
INPUTS
INPUTS/OUTPUTS
OUTPUTS
CLEAR
FUNCTION
SELECTED
OUTPUT
CONTROL
CLOCK
SERIAL
A/QA
H/QH
QA’
QH’
S1
S0
G1*
G2*
SL
SR
Z
L
L
L
H
H
H
H
H
H
H
L
X
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
X
L
L
L
L
L
L
L
X
X
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
Z
L
L
Z
L
L
L
L
L
L
L
L
CLEAR
HOLD
QA0
H
L
QBn
QBn
a
QH0
QGn
QGn
H
L
h
QA0
H
L
QBn
QBn
a
QH0
QGn
QGn
H
L
h
SHIFT
RIGHT
SHIFT
LEFT
LOAD
相關(guān)PDF資料
PDF描述
74AC299 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR
74AC299B 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR
74AC299M 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR
74AC299PC 8-Input Universal Shift/Storage Register
74AC299MTC 8-Input Universal Shift/Storage Register
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