參數(shù)資料
型號(hào): 74AC191SJX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Microprocessor-Compatible, 14-Bit DACs
中文描述: AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16
封裝: 5.30 MM, EIAJ TYPE2, SOP-16
文件頁(yè)數(shù): 1/10頁(yè)
文件大?。?/td> 115K
代理商: 74AC191SJX
1999 Fairchild Semiconductor Corporation
DS009940
www.fairchildsemi.com
November 1988
Revised November 1999
7
74AC191
Up/Down Counter with Preset and Ripple Clock
General Description
The AC191 is a reversible modulo 16 binary counter. It fea-
tures synchronous counting and asynchronous presetting.
The preset feature allows the AC191 to be used in pro-
grammable dividers. The Count Enable input, the Terminal
Count output and the Ripple Clock output make possible a
variety of methods of implementing multistage counters. In
the counting modes, state changes are initiated by the ris-
ing edge of the clock.
Features
I
I
CC
reduced by 50%
I
High speed—133 MHz typical count frequency
I
Synchronous counting
I
Asynchronous parallel load
I
Cascadable
I
Outputs source/sink 24 mA
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter
X
to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT
is a trademark of Fairchild Semiconductor Corporation.
Order Number
74AC191SC
74AC191SJ
74AC191MTC
74AC191PC
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150
Narrow Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300
Wide
Pin Names
Description
CE
CP
P
0
P
3
PL
Count Enable Input
Clock Pulse Input
Parallel Data Inputs
Asynchronous Parallel Load Input
U /D
Q
0
Q
3
RC
TC
Up/Down Count Control Input
Flip-Flop Outputs
Ripple Clock Output
Terminal Count Output
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參數(shù)描述
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