參數(shù)資料
型號(hào): 74AC08SJX
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 10/10頁(yè)
文件大?。?/td> 0K
描述: IC GATE AND QUAD 2INPUT 14SOP
標(biāo)準(zhǔn)包裝: 2,000
系列: 74AC
邏輯類(lèi)型: 與門(mén)
電路數(shù): 4
輸入數(shù): 2
電源電壓: 2 V ~ 6 V
電流 - 靜態(tài)(最大值): 2µA
輸出電流高,低: 24mA,24mA
邏輯電平 - 低: 0.9 V ~ 1.65 V
邏輯電平 - 高: 2.1 V ~ 3.85 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 7.5ns @ 5V,50pF
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
供應(yīng)商設(shè)備封裝: 14-SOIC
封裝/外殼: 14-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
1988 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74AC08, 74ACT08 Rev. 1.5.1
9
74A
C08,
74A
CT08
Quad
2-Input
AND
Gate
Physical Dimensions (Continued)
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specications do not expand the terms of Fairchild’s worldwide terms and conditions,
specically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
14
8
7
1
NOTES: UNLESS OTHERWISE SPECIFIED
A)
THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C)
DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
6.60
6.09
8.12
7.62
0.35
0.20
19.56
18.80
3.56
3.30
5.33 MAX
0.38 MIN
1.77
1.14
0.58
0.35
2.54
3.81
3.17
8.82
(1.74)
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