參數(shù)資料
型號： 74ABTH16841ADL
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： 20-bit bus interface latch 3-State
中文描述： ABT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56
封裝： 7.50 MM, PLASTIC, SOT-371-1, SSOP3-56
文件頁數(shù)： 5/10頁
文件大?。?/td> 82K
代理商： 74ABTH16841ADL
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
1998 Feb 27
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
°
C
T
amb
= -40
°
C
°
C
Min
UNIT
Min
Typ
–0.9
2.9
3.4
2.4
0.42
0.13
Max
–1.2
Max
–1.2
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= -18mA
V
CC
= 4.5V; I
OH
= -3mA; V
I
= V
IL
or V
IH
V
CC
= 5.0V; I
OH
= -3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= -32mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
V
V
V
V
V
V
2.5
3.0
2.0
2.5
3.0
2.0
V
OH
High-level output voltage
V
OL
V
RST
Low-level output voltage
Power-up output voltage
3
0.55
0.55
0.55
0.55
Input leakage current
In ut leakage current
74ABT16841A
I
V
= 5.5V; V
= V
or GND
CC
I
±
0.01
±
1
±
1.0
A
μ
I
CC
Input leakage current
74ABTH16841A
V
CC
= 5.5V; V
I
= V
CC
or GND
V
CC
= 5.5V; V
I
= V
CC
V
CC
= 5.5V; V
I
= 0
V
CC
= 4.5V; V
I
= 0.8V
V
CC
= 4.5V; V
I
= 2.0V
V
CC
= 5.5V; V
I
= 0 to 5.5V
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
CC
= 2.1V; V
O
= 0.5V; V
I
= GND or V
CC
;
V
OE
= Don’t care
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3-State; V
I
= GND or V
CC
V
CC
= 5.5V; one input at 3.4V, other inputs at
V
CC
or GND
Control pins
±
0.01
0.01
–2
±
1
1
–3
±
1
1
–5
μ
A
μ
A
μ
A
I
I
Data pins
Data ins
5
Bus Hold current inputs
6
74ABTH16841A
35
–75
±
800
35
–75
I
HOLD
μ
A
I
OFF
Power-off leakage current
±
5.0
±
100
±
100
μ
A
I
PU/PD
Power-up/down 3-State
output current
4
3-State output High current
3-State output Low current
Output High leakage current
Output current
1
±
5.0
±
50
±
50
μ
A
I
OZH
I
OZL
I
CEX
I
O
I
CCH
I
CCL
I
CCZ
5.0
–5.0
5.0
–70
0.5
10
0.5
10
–10
50
–180
1
19
1
10
–10
50
–180
1
19
1
μ
A
μ
A
μ
A
mA
mA
mA
mA
–50
–50
Quiescent supply current
I
CC
Additional supply current per
input pin
2
0.2
1
1
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V
±
10% a
transition time of up to 100
μ
sec is permitted.
5. Unused pins at V
CC
or GND.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
TYP
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
±
0.5V
MIN
UNIT
MIN
MAX
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
nDx to nQx
2
1.1
1.5
3.1
2.2
4.1
3.1
1.1
1.5
4.9
3.6
ns
Propagation delay
nLE to nQx
1
1.5
1.0
2.5
2.1
3.3
2.8
1.5
1.0
3.7
3.1
ns
Output enable time
to High and Low level
4
5
1.2
1.2
2.4
2.2
3.2
2.9
1.2
1.2
4.0
3.6
ns
Output disable time
from High and Low level
4
5
1.8
1.5
3.0
2.5
4.0
3.2
1.8
1.5
4.9
3.7
ns
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