參數(shù)資料
型號: 74ABTH16841ADGG
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 20-bit bus interface latch 3-State
中文描述: ABT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56
封裝: 6.10 MM, PLASTIC, SOT-364-1, TSSOP2-56
文件頁數(shù): 6/10頁
文件大?。?/td> 82K
代理商: 74ABTH16841ADGG
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
1998 Feb 27
6
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
Min
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
±
0.5V
Min
UNIT
Typ
Max
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
Setup time, High or Low
nDx to nLE
3
2.0
1.0
1.0
0.4
2.0
1.0
ns
Hold time, High or Low
nDx to nLE
3
2.0
2.0
–0.3
–0.7
2.0
2.0
ns
nLE pulse width High
1
2.9
1.9
2.9
ns
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
t
w
(H)
t
PHL
t
PLH
nLE
nQx
SA00078
V
M
V
M
V
M
V
M
V
M
3.0V or V
CC
whichever
is less
0V
V
OH
V
OL
Waveform 1. Propagation Delay, Latch Enable Input to
Output, and Enable Pulse Width
nDx INPUT
V
M
t
PLH
t
PHL
nQx OUTPUT
V
M
V
M
V
M
SA00079
3.0V or V
CC
whichever
is less
0V
3.0V or V
CC
whichever
is less
0V
Waveform 2. Propagation Delay for Data to Outputs
NOTE
:
The shaded areas indicate when the input is
permitted to change for predictable output performance.
ééé
t
s
(H)
éééééééé
éééééééé
t
h
(H)
t
h
(L)
M
nDx
V
M
V
M
nLE
t
s
(L)
SA00080
0V
0V
3.0V or V
CC
whichever
is less
3.0V or V
CC
whichever
is less
Waveform 3. Data Setup and Hold Times
V
Y
V
M
V
M
V
M
nQx
t
PZH
t
PHZ
SH00007
nOE
0V
V
OH
0V
3.0V or V
CC
whichever
is less
Waveform 4. 3–State Output Enable Time to High Level
and Output Disable Time from High Level
V
X
V
OL
V
M
V
M
V
M
nQx
t
PZL
t
PLZ
SH00008
nOE
0V
0V
3.0V or V
CC
3.0V or V
CC
whichever
is less
Waveform 5. 3–State Output Enable Time to Low Level and
Output Disable Time from Low Level
相關(guān)PDF資料
PDF描述
74ABTH16841ADL 20-bit bus interface latch 3-State
74ABT16899DL 18-bit latched transceiver with 16-bit parity generator/checker 3-State
74ABTH16899DL 18-bit latched transceiver with 16-bit parity generator/checker 3-State
74ABT16899 18-bit latched transceiver with 16-bit parity generator/checker 3-State
74ABTH16899 18-bit latched transceiver with 16-bit parity generator/checker (3-State)(帶16位奇偶發(fā)生器/校驗(yàn)器的18位鎖存收發(fā)器(三態(tài)))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74ABTH16899DGG,112 功能描述:總線收發(fā)器 18-BIT LATCH XCVR W/PAR/BUS 3S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ABTH16899DGG,118 功能描述:總線收發(fā)器 18-BIT LATCH XCVR W/PAR/BUS 3S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ABTH16899DL,112 功能描述:總線收發(fā)器 18-BIT LATCH XCVR W/PAR/BUS 3S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ABTH16899DL,118 功能描述:總線收發(fā)器 18-BIT LATCH XCVR W/PAR/BUS 3S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ABTH182502APMG4 功能描述:特定功能邏輯 Scan Test Devices RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube