參數資料
型號： 74ABTH16841A
廠商： NXP Semiconductors N.V.
英文描述： 20-bit bus interface latch (3-State)(20位總線接口鎖存器（三態(tài)）)
中文描述： 20位總線接口鎖存器（3態(tài)）（20位總線接口鎖存器（三態(tài)））
文件頁數： 2/10頁
文件大?。?/td> 82K
代理商： 74ABTH16841A
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
2
1998 Feb 27
853-1797 19025
FEATURES
High speed parallel latches
Live insertion/extraction permitted
Extra data width for wide address/data paths or buses carrying
parity
Power-up 3-State
74ABTH16841A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Power-up reset
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT16841A Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT16841A consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is High. This allows asynchronous operation, as
the output transition follows the data in transition. On the nLE
High-to-Low transition, the data that meets the setup and hold time
is latched.
Data appears on the bus when the Output Enable (nOE) is Low.
When nOE is High the output is in the High-impedance state.
Two options are available, 74ABT16841A which does not have the
bus-hold feature and 74ABTH16841A which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
°
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
nDx to nQx
C
L
= 50pF; V
CC
= 5V
3.1
2.2
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
OUT
Output capacitance
V
O
= 0V or V
CC
; 3-State
7
pF
I
CCZ
Quiescent supply current
Outputs disabled; V
CC
= 5.5V
500
μ
A
I
CCL
Outputs LOW; V
CC
= 5.5V
10
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
74ABT16841A DL
BT16841A DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°
C to +85
°
C
74ABT16841A DGG
BT16841A DGG
SOT364-1
56-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
74ABTH16841A DL
BH16841A DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°
C to +85
°
C
74ABTH16841A DGG
BH16841A DGG
SOT364-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
1D0 – 1D9
2D0 – 2D9
Data inputs
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1Q0 – 1Q9
2Q0 – 2Q9
Data outputs
1, 28
1OE, 2OE
Output enable inputs (active-Low)
56, 29
1LE, 2LE
Latch enable inputs (active rising edge)
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
相關PDF資料
PDF描述
74ABTH16841ADGG 20-bit bus interface latch 3-State
74ABTH16841ADL 20-bit bus interface latch 3-State
74ABT16899DL 18-bit latched transceiver with 16-bit parity generator/checker 3-State
74ABTH16899DL 18-bit latched transceiver with 16-bit parity generator/checker 3-State
74ABT16899 18-bit latched transceiver with 16-bit parity generator/checker 3-State
相關代理商/技術參數
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74ABTH16899DGG,112 功能描述:總線收發(fā)器 18-BIT LATCH XCVR W/PAR/BUS 3S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ABTH16899DGG,118 功能描述:總線收發(fā)器 18-BIT LATCH XCVR W/PAR/BUS 3S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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