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參數(shù)資料
| 型號(hào)： | 74ABT843PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 9-bit interface latch with set and reset 3-State |
| 中文描述： | ABT SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24 |
| 文件頁(yè)數(shù)： | 5/14頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | 74ABT843PWDH |
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Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
1998 Jan 16
5
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
Max
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
OH
High-level output current
–32
mA
I
OL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate
0
10
ns/V
T
amb
Operating free-air temperature range
–40
+85
°
C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
°
C
T
amb
= –40
°
C
to +85
°
C
UNIT
Min
Typ
Max
Min
Max
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
–0.9
–1.2
–1.2
V
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
2.5
2.9
2.5
V
V
OH
High–level output voltage
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
3.0
3.4
3.0
V
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
2.0
2.4
2.0
V
V
OL
Low–level output voltage
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
0.42
0.55
0.55
V
V
RST
Power–up output low
voltage
3
V
CC
= 5.5V; I
O
= 1mA; V
I
= V
CC
or GND
0.13
0.55
0.55
V
I
I
Input leakage current
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
= 2.0V; V
O
= 0.5V; V
OE
= V
CC
; V
I
=
GND or V
CC
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
±
0.01
±
5.0
±
1.0
±
100
±
1.0
±
100
μ
A
μ
A
I
OFF
Power-off leakage current
I
PU/
I
PD
Power-up/down 3–state
output current
4
±
5.0
±
50
±
50
μ
A
I
OZH
3-State output High current
5.0
50
50
μ
A
I
OZL
3-State output Low current
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
–5.0
–50
–50
μ
A
I
CEX
Output high leakage current
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
5.0
50
50
μ
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
–50
–80
–180
–50
–180
mA
I
CCH
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
0.5
250
250
μ
A
I
CCL
Quiescent supply current
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
25
34
34
mA
I
CCZ
V
CC
= 5.5V; Outputs 3-State;
V
I
CC
0.5
250
250
μ
A
I
CC
Additional supply current per
input pin
2
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
0.5
1.5
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip–flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. For V
CC
= 2.1V to V
CC
= 5V
transition time of up to 100
μ
sec is permitted.
10%, a
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