參數(shù)資料
型號： 74ABT834N
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： Octal inverting transceiver with parity generator/checker 3-State
中文描述： ABT SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDIP24
封裝： 0.300 INCH, PLASTIC, DIP-24
文件頁數(shù)： 1/7頁
文件大?。?/td> 58K
代理商： 74ABT834N
Philips Semiconductors Advanced BiCMOS Products
Objective specification
74ABT834
Octal inverting transceiver with parity
generator/checker (3–State)
1
June 9, 1992
FEATURES
Low static and dynamic power dissipation
with high speed and high output drive
Open–collector ERROR output
Output capability: +64mA/–32mA
Latch–up protection exceeds 500mA per
Jedec JC40.2 Std 17
ESD protection exceeds 2000 V per MIL
STD 883C Method 3015.6 and 200 V per
Machine Model
Power up/down 3–State
DESCRIPTION
The 74ABT834 high–performance BiCMOS
device combines low static and dynamic
QUICK REFERENCE DATA
power dissipation with high speed and high
output drive.
The 74ABT834 is an octal inverting
transceiver with a parity generator/checker
and is intended for bus–oriented applications.
When Output Enable A (OEA) is High, it will
place the A outputs in a high impedance
state. Output Enable B (OEB) controls the B
outputs in the same way.
The parity generator creates an odd parity
output (PARITY) when OEB is Low. When
OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity.
When an error is detected, the error data is
sent to the input of a storage register. If a
Low–to–High transition happens at the clock
input (CP), the error data is stored in the
register and the Open–collector error flag
(ERROR) will go Low. The error flag register
is cleared with a Low pulse on the CLEAR
input.
If both OEA and OEB are Low, data will flow
from the A bus to the B bus and the part is
forced into an error condition which creates
an inverted PARITY output. This error
condition can be used by the designer for
system diagnostics.
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
°
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
C
L
= 50pF; V
CC
= 5V
3.4
ns
t
PLH
t
PHL
Propagation delay
An to PARITY
C
L
= 50pF; V
CC
= 5V
7.4
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
OUT
Output capacitance
V
I
= 0V or V
CC
7
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
=5.5V
50
μ
A
ORDERING INFORMATION
PACKAGES
CONDITIONS
T
amb
= 25
°
C; GND = 0V
–40
°
C to +85
°
C
–40
°
C to +85
°
C
ORDER CODE
24–pin plastic DIP (300mil)
74ABT834N
24–pin plastic SOL (300mil)
74ABT834D
PIN CONFIGURATION
LOGIC SYMBOL
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
V
CC
GND
CLEAR
OEA
B0
B1
B2
B3
B6
B7
PARITY
OEB
A0
A1
A2
A3
A4
A5
A6
A7
ERROR
CP
B4
B5
OEB
OEA
CLEAR
14
1
11
15
10
PARITY
ERROR
TOP VIEW
CP
13
2
3
4
5
6
7
8
9
A0 A1 A2 A3 A4 A5 A6 A7
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 19 18 17 16
相關(guān)PDF資料
PDF描述
74ABT841 10-bit bus interface latch (3-State)(10位總線接口鎖存器（三態(tài)）)
74ABT841D 10-bit bus interface latch 3-State
74ABT841DB 10-bit bus interface latch 3-State
74ABT841N Octal buffers and line drivers 20-SOIC 0 to 70
74ABT841PW 10-bit bus interface latch 3-State
相關(guān)代理商/技術(shù)參數(shù)
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74ABT841D 功能描述:閉鎖 10-BIT BUS INTERFACE LATCH 3-S RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
74ABT841D,602 功能描述:閉鎖 10-BIT BUS INTERFACE RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
74ABT841D,623 功能描述:閉鎖 10-BIT BUS INTERFACE RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
74ABT841DB 功能描述:閉鎖 10-BIT BUS INTERFACE LATCH 3-S RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
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