參數(shù)資料
型號: 74ABT657PW,118
廠商: NXP Semiconductors
文件頁數(shù): 16/17頁
文件大?。?/td> 0K
描述: IC TRANSCVR 3ST 8BIT 24TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,500
系列: 74ABT
邏輯類型: 收發(fā)器,非反相
元件數(shù): 1
每個元件的位元數(shù): 8
輸出電流高,低: 32mA,64mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
其它名稱: 74ABT657PW-T
74ABT657PW-T-ND
935178900118
74ABT657_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
8 of 17
NXP Semiconductors
74ABT657
Octal transceiver with parity generator/checker; 3-state
10. Dynamic characteristics
[1]
These delay times reect the 3-state recovery time only and do not include the delay through the buffers and the parity check circuitry
which affect the ERROR output. To ensure valid information at the ERROR pin, time must be allowed for the signal to propagate
through the drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output. Valid data at the
ERROR pin
≥ (B to A) + (A to PARITY).
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see Figure 9.
Symbol Parameter
Conditions
25
°C; V
CC = 5.0 V
40 °C to +85 °C;
VCC = 5.0 V ± 0.5 V
Unit
Min
Typ
Max
Min
Max
tPLH
LOW to HIGH
propagation delay
An to Bn or Bn to An; see Figure 6
1.1
2.5
4.1
1.1
4.6
ns
An to PARITY; see Figure 5 and 6
2.5
5.1
6.7
2.5
8.1
ns
ODD/EVEN to PARITY and ERROR;
see Figure 5 and 6
1.7
3.5
4.6
1.7
5.3
ns
Bn to ERROR; see Figure 5 and 6
3.9
7.3
10.2
3.9
12.3
ns
PARITY to ERROR; see Figure 5 and 6
2.7
4.5
5.9
2.7
7.7
ns
tPHL
HIGH to LOW
propagation delay
An to Bn or Bn to An; see Figure 6
1.2
3.0
3.9
1.2
4.3
ns
An to PARITY; see Figure 5 and 6
2.8
5.0
7.4
2.8
8.9
ns
ODD/EVEN to PARITY and ERROR;
see Figure 5 and 6
1.9
3.7
5.1
1.9
5.8
ns
Bn to ERROR; see Figure 5 and 6
4.0
7.9
10.5
4.0
12.9
ns
PARITY to ERROR; see Figure 5 and 6
3.2
5.2
6.7
3.2
8.1
ns
tPZH
OFF-state to HIGH
propagation delay
see Figure 7 and 8
1.3
3.6
5.5
1.3
6.5
ns
tPZL
OFF-state to LOW
propagation delay
see Figure 7 and 8
1.9
4.2
5.3
1.9
6.5
ns
tPHZ
HIGH to OFF-state
propagation delay
see Figure 7 and 8
2.4
3.6
5.6
2.4
6.2
ns
tPLZ
LOW to OFF-state
propagation delay
see Figure 7 and 8
2.2
3.4
7.3
2.2
7.8
ns
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