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參數(shù)資料
| 型號： | 74ABT652CSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Single 8-bit Bus Transceiver |
| 中文描述： | ABT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 0.300 INCH, MS-013, SOIC-24 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 92K |
| 代理商： | 74ABT652CSCX |
www.fairchildsemi.com
2
7
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW to HIGH Clock Transition
Note 1:
The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs.
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples in Figure 1 demonstrate the four fundamen-
tal bus-management functions that can be performed with
the ABT652.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flop by LOW to HIGH transitions at the
appropriate Clock Inputs (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer mode, it is also possible to store data
without using the internal D flip-flops by simultaneously
enabling OEAB and OEBA. In this configuration each Out-
put reinforces its Input. Thus when all other data sources to
the two sets of bus lines are in a HIGH impedance state,
each set of bus lines will remain at its last state.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Inputs/Outputs (Note 1)
A
0
thru A
7
Input
Operating Mode
OEAB
OEBA
H
H
H
H
X
L
L
L
H
H
L
CPAB
CPBA
SAB
SBA
B
0
thru B
7
Input
L
L
X
H
L
L
L
L
H
H
H
H or L H or L
H or L
X
X
X
H or L
H or L H or L
X
X
X
X
X
X
X
X
L
H
H
X
X
X
X
X
X
L
H
X
X
H
Isolation
Store A and B Data
H or L
X
H or L
X
X
Input
Input
Not Specified Input
Output
Output
Not Specified Store A, Hold B
Output
Store A in Both Registers
Hold A, Store B
Input
Store B in Both Registers
Input
Real-Time B Data to A Bus
Store B Data to A Bus
Output
Real-Time A Data to B Bus
Stored A Data to B Bus
Output
Stored A Data to B Bus and
Stored B Data to A Bus
Input
Output
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