參數(shù)資料
型號(hào): 74ABT652ADB,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 16/19頁(yè)
文件大小: 0K
描述: IC TRANSCVR 8BIT N-INV 24SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 59
系列: 74ABT
邏輯類型: 收發(fā)器,反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
輸出電流高,低: 32mA,64mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 管件
其它名稱: 74ABT652ADB
74ABT652ADB-ND
935192700112
74ABT652A_2
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 12 March 2010
6 of 19
NXP Semiconductors
74ABT652A
Octal transceiver/register; non-inverting; 3-state
6.
Functional description
6.1 Function table
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH clock transition.
[2]
The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.
[3]
If both select controls (SAB and SBA) are LOW, then clocks can occur simultaneously. If either select control is HIGH, the clocks must
be staggered in order to load both registers.
Figure 3 demonstrates the four fundamental bus-management functions that can be
performed with the 74ABT652A.
The select pins determine whether data is stored or transferred through the device in real
time.
The output enable pins determine the direction of the data ow.
Table 3.
Function table [1]
Inputs
Data I/O
Operating mode
OEAB
OEBA
CPAB
CPBA
SAB
SBA
An
Bn
L
H
H or L
X
input
isolation
LH
↑↑
X
input
store A and B data
XH
H or L
X
input
unspecied
output [2]
store A, hold B
HH
↑↑
X
input
unspecied
output [2]
store A in both registers
L
X
H or L
X
unspecied
output [2]
input
hold A, store B
LL
↑↑
X
unspecied
output [2]
input
store B in both registers
L
X
L
output
input
real time B data to A bus
L
X
H or L
X
H
output
input
stored B data to A bus
H
X
L
X
input
output
real time A data to B bus
H
H or L
X
H
X
input
output
store A data to B bus
H
L
H or L
H
output
stored A data to B bus;
stored B data to A bus
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