參數(shù)資料
型號(hào): 74ABT652AD,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 19/19頁(yè)
文件大?。?/td> 0K
描述: IC TRANSCEIVER 8BIT N-INV 24SOIC
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 30
系列: 74ABT
邏輯類(lèi)型: 收發(fā)器,反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
輸出電流高,低: 32mA,64mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SO
包裝: 管件
其它名稱(chēng): 74ABT652AD
74ABT652AD-ND
935192690112
74ABT652A_2
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 12 March 2010
9 of 19
NXP Semiconductors
74ABT652A
Octal transceiver/register; non-inverting; 3-state
10. Dynamic characteristics
[1]
This data sheet limit may vary among suppliers.
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see Figure 12.
Symbol Parameter
Conditions
25
°C; V
CC = 5.0 V
40 °C to +85 °C;
VCC = 5.0 V ± 0.5 V
Unit
Min
Typ
Max
Min
Max
fmax
maximum
frequency
125
300
-
125
-
MHz
tPLH
LOW to HIGH
propagation delay
CPAB to Bn or CPBA to An; see Figure 6
2.2
3.7
5.1
2.2
5.6
ns
An to Bn or Bn to An; see Figure 7
1.5
3.0
4.3
1.5
4.8
ns
SAB to Bn or SBA to An; see Figure 8
1.5
3.5
5.1
1.5
6.5
ns
tPHL
HIGH to LOW
propagation delay
CPAB to Bn or CPBA to An; see Figure 6
1.7
4.3
5.1
1.7
5.6
ns
An to Bn or Bn to An; see Figure 7
1.5
3.6
4.6
1.5
5.4
ns
SAB to Bn or SBA to An; see Figure 8
1.5
4.2
1.5
5.9
ns
tPZH
OFF-state to HIGH
propagation delay
OEBA to An; see Figure 10
2
3.2
4.6
2
5.8
ns
OEAB to Bn; see Figure 10
2
3.5
6.1
2
6.5
ns
tPZL
OFF-state to LOW
propagation delay
OEBA to An; see Figure 11
3
4.5
6.8
3
8.5
ns
OEAB to Bn; see Figure 11
3
4.7
6.5
3
7.4
ns
tPHZ
HIGH to OFF-state
propagation delay
OEBA to An; see Figure 10
1.5
3.9
1.5
5.3[1]
ns
OEAB to Bn; see Figure 10
1.5
3.8
1.5
5.5
ns
tPLZ
LOW to OFF-state
propagation delay
OEBA to An; see Figure 11
1.5
2.9
3.8
1.5
4.1
ns
OEAB to Bn; see Figure 11
1.5
3.0
4.4
1.5
5.1
ns
tsu(H)
set-up time HIGH
An to CPAB, Bn to CPBA; see Figure 9
3.0
0.7
-
3.0
-
ns
tsu(L)
set-up time LOW
An to CPAB, Bn to CPBA; see Figure 9
3.0
0.7
-
3.0
-
ns
th(H)
hold time HIGH
An to CPAB, Bn to CPBA; see Figure 9
0.0
0.5
-
0.0
-
ns
th(L)
hold time LOW
An to CPAB, Bn to CPBA; see Figure 9
0.0
0.5
-
0.0
-
ns
tWH
pulse width HIGH
CPAB, CPBA; see Figure 6
4.0
1.0
-
4.0
-
ns
tWL
pulse width LOW
CPAB, CPBA; see Figure 6
4.0
1.0
-
4.0
-
ns
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