參數(shù)資料
型號(hào): 74ABT652
廠商: Fairchild Semiconductor Corporation
英文描述: Octal Transceivers and Registers with 3-STATE Outputs
中文描述: 八路收發(fā)器和寄存器具有三態(tài)輸出
文件頁數(shù): 5/10頁
文件大小: 92K
代理商: 74ABT652
5
www.fairchildsemi.com
7
DC Electrical Characteristics
(SOIC package)
Note 7:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 8:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 9:
Max number of data inputs (n) switching. n
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package)
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
C
L
=
50 pF, R
L
=
500
T
A
=
25
°
C (Note 7)
T
A
=
25
°
C (Note 7)
T
A
=
25
°
C (Note 8)
T
A
=
25
°
C (Note 9)
T
A
=
25
°
C (Note 9)
V
OLP
V
OLV
V
OHV
V
IHD
V
ILD
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
0.6
0.9
3.0
1.8
0.8
0.8
V
V
5.0
5.0
1.2
2.5
2.2
V
V
V
5.0
5.0
5.0
0.4
Symbol
Parameter
T
A
=
+
25
°
C
V
CC
=
+
5.0V
C
L
=
50 pF
Typ
T
A
=
40
°
C to
+
85
°
C
V
CC
=
4.5V–5.5V
C
L
=
50 pF
Min
200
1.7
1.7
Units
Min
200
1.7
1.7
Max
Max
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Max Clock Frequency
Propagation Delay
Clock to Bus
MHz
ns
3.0
3.4
4.9
4.9
4.9
4.9
Propagation Delay
Bus to Bus
Propagation Delay
1.5
1.5
1.5
2.6
3.0
3.0
4.5
4.5
5.0
1.5
1.5
1.5
4.5
4.5
5.0
ns
ns
SBA or SAB to A
n
to B
n
Enable Time
1.5
1.5
1.5
3.4
3.3
3.7
5.0
5.5
5.5
1.5
1.5
1.5
5.0
5.5
5.5
ns
OEBA or OEAB to A
n
or B
n
Disable Time
1.5
1.5
3.7
3.3
6.0
6.0
1.5
1.5
6.0
6.0
ns
OEBA or OEAB to A
n
or B
n
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