參數(shù)資料
型號(hào): 74ABT16833DGGRG4
廠商: Texas Instruments
文件頁數(shù): 13/13頁
文件大?。?/td> 0K
描述: IC DUAL 8-9BIT BUS TXRX 56-TSSOP
標(biāo)準(zhǔn)包裝: 2,000
系列: 74ABT
邏輯類型: 收發(fā)器,非反相
元件數(shù): 2
每個(gè)元件的位元數(shù): 8
輸出電流高,低: 32mA,64mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
SN54ABT16833, SN74ABT16833
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
(see Note A)
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
tPHL (see Note E)
tPLH (see Note F)
7 V
ERR
S1
1.5 V
th
tsu
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPLH
VOH
VOL
1.5 V
3 V
0 V
1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 , tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPHL is measured at 1.5 V.
F. tPLH is measured at VOL + 0.3 V.
Figure 1. Load Circuit and Voltage Waveforms
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