參數(shù)資料
型號： 74ABT162501DLRG4
廠商： Texas Instruments
文件頁數(shù)： 1/10頁
文件大小： 0K
描述： IC UNIV BUS TXRX 18BIT 56SSOP
標準包裝： 1,000
系列： 74ABT
邏輯類型： 通用總線收發(fā)器
電路數(shù)： 18 位
輸出電流高，低： 32mA，64mA; 12mA，12mA
電源電壓： 4.5 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 56-SSOP
包裝： 帶卷 (TR)
SN54ABT162501, SN74ABT162501
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS243E – SEPTEMBER 1992 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Members of the Texas Instruments
Widebus
Family
D B-Port Outputs Have Equivalent 25-
Series Resistors, So No External Resistors
Are Required
D State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
D UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
D High-Impedance State During Power Up
and Power Down
D Flow-Through Architecture Optimizes PCB
Layout
D Latch-Up Performance Exceeds 500 mA
Per JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
These 18-bit universal bus transceivers consist of
storage elements that can operate either as
D-type latches or D-type flip-flops to allow data
flow in transparent or clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the
outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-
series resistors
to reduce overshoot and undershoot.
SN54ABT162501 ...WD PACKAGE
SN74ABT162501 . . . DGG OR DL PACKAGE
(TOP VIEW)
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OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
Copyright
1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Widebus, EPIC-
ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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