參數(shù)資料
型號: 7429FCT520ATD
廠商: Integrated Device Technology, Inc.
英文描述: MULTILEVEL PIPELINE REGISTERS
中文描述: 多級管道登記冊
文件頁數(shù): 5/7頁
文件大?。?/td> 93K
代理商: 7429FCT520ATD
IDT29FCT520AT/BT/CT/DT, 521AT/BT/CT/DT
MULTILEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.2
5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT520AT/521AT
Com'l.
Min
.
(2)
Max.
FCT520BT/521BT
Com'l.
Min
.
(2)
Max.
Mil.
Mil.
Symbol
t
PHL
t
PLH
t
PHL
t
PLH
t
SU
Parameter
Condition
(1)
C
L
= 50pF
R
L
= 500
Min
.
(2)
Max.
Min
.
(2)
Max.
Unit
Propagation Delay
CLK to Yn
Propagation Delay
S
0
or S
1
to Yn
Set-up Time, HIGH or LOW
Dn to CLK
Hold Time, HIGH or LOW
Dn to CLK
Set-up Time, HIGH or LOW
I
0
or I
1
to CLK
Hold Time, HIGH or LOW
I
0
or I
1
to CLK
Output Disable Time
2.0
14.0
2.0
16.0
2.0
7.5
2.0
8.0
ns
2.0
13.0
2.0
15.0
2.0
7.5
2.0
8.0
ns
5.0
6.0
2.5
2.8
ns
t
H
2.0
2.0
2.0
2.0
ns
t
SU
5.0
6.0
4.0
4.5
ns
t
H
2.0
2.0
2.0
2.0
ns
t
PHZ
t
PLZ
t
PZH
t
PZL
t
W
1.5
12.0
1.5
13.0
1.5
7.0
1.5
7.5
ns
Output Enable Time
1.5
15.0
1.5
16.0
1.5
7.5
1.5
8.0
ns
Clock Pulse Width
HIGH or LOW
7.0
8.0
5.5
6.0
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum units are guaranteed but not tested on Propagation Delays.
2619 tbl 08
2619 tbl 07
FCT520CT/521CT
Com'l.
Min
.
(2)
Max.
FCT520DT/521DT
Com'l.
Min
.
(2)
Max.
Mil.
Mil.
Symbol
t
PHL
t
PLH
t
PHL
t
PLH
t
SU
Parameter
Condition
(1)
C
L
= 50pF
R
L
= 500
Min
.
(2)
Max.
Min
.
(2)
Max.
Unit
Propagation Delay
CLK to Yn
Propagation Delay
S
0
or S
1
to Yn
Set-up Time, HIGH or LOW
Dn to CLK
Hold Time, HIGH or LOW
Dn to CLK
Set-up Time, HIGH or LOW
I
0
or I
1
to CLK
Hold Time, HIGH or LOW
I
0
or I
1
to CLK
Output Disable Time
2.0
6.0
2.0
7.0
2.0
5.2
ns
2.0
6.0
2.0
7.0
2.0
4.8
ns
2.5
2.8
1.5
ns
t
H
2.0
2.0
1.0
ns
t
SU
4.0
4.5
2.0
ns
t
H
2.0
2.0
1.0
ns
t
PHZ
t
PLZ
t
PZH
t
PZL
t
W
1.5
6.0
1.5
6.0
1.5
4.8
ns
Output Enable Time
1.5
6.0
1.5
7.0
1.5
4.0
ns
Clock Pulse Width
HIGH or LOW
(3)
5.5
6.0
3.0
ns
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