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參數(shù)資料
| 型號： | 74240 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Octal 3-STATE Buffer/Line Driver/Line Receiver |
| 中文描述： | 八路三態(tài)緩沖器/線路驅(qū)動器/線接收器 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 72K |
| 代理商： | 74240 |
2000 Fairchild Semiconductor Corporation
DS006411
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74LS240 DM74LS241
Octal 3-STATE Buffer/Line Driver/Line Receiver
General Description
These buffers/line drivers are designed to improve both the
performance and PC board density of 3-STATE buffers/
drivers employed as memory-address drivers, clock driv-
ers, and bus-oriented transmitters/receivers. Featuring
400 mV of hysteresis at each low current PNP data line
input, they provide improved noise rejection and high
fanout outputs and can be used to drive terminated lines
down to 133
.
Features
I
3-STATE outputs drive bus lines directly
I
PNP inputs reduce DC loading on bus lines
I
Hysteresis at data inputs improves noise margins
I
Typical I
OL
(sink current)
24 mA
I
Typical I
OH
(source current)
15 mA
I
Typical propagation delay times
Inverting
10.5 ns
Noninverting
12 ns
I
Typical enable/disable time 18 ns
I
Typical power dissipation (enabled)
Inverting
130 mW
Noninverting
135 mW
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
DM74LS240
DM74LS241
Order Number
DM74LS240WM
DM74LS240SJ
DM74LS240N
DM74LS241WM
DM74LS241N
Package Number
M20B
M20D
N20A
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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